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1.发明授权公开(公告)号：US10944418B2
公开(公告)日：2021-03-09
申请号：US16188217
申请日：2018-11-12
Applicant: MEDIATEK INC.
Inventor： Ting-Yang Wang , Hung-Yi Hsieh , Tzu-An Wei , Tien-Yu Lo
Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.
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2.发明申请公开(公告)号：US20190238151A1
公开(公告)日：2019-08-01
申请号：US16188217
申请日：2018-11-12
Applicant: MEDIATEK INC.
Inventor： Ting-Yang Wang , Hung-Yi Hsieh , Tzu-An Wei , Tien-Yu Lo
IPC: H03M3/00
CPC classification number: H03M3/32 , H03M1/007 , H03M1/38 , H03M3/30 , H03M3/426 , H03M3/436 , H03M3/464
Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.
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3.发明授权System and method for measuring the DC-transfer characteristic of an analog-to-digital converter 有权用于测量模数转换器的直流传递特性的系统和方法公开(公告)号：US09584146B2
公开(公告)日：2017-02-28
申请号：US14886545
申请日：2015-10-19
Applicant: MediaTek Inc.
Inventor： Frank Op 't Eynde , Nathan Egan , Khurram Muhammad , Tien-Yu Lo , Chi-Lun Lo , Michael A. Ashburn
CPC classification number: H03M1/109 , H03M1/1038 , H03M1/12 , H03M3/50
Abstract: Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.
Abstract translation: 描述了用于测量和补偿模数转换器的直流传递特性的系统和方法。 包括Σ-Δ调制器的测试信号发生器可以向ADC提供校准信号。 来自ADC的输出可以用陷波滤波器滤波，以抑制由Σ-Δ调制器引入的离散频率的量化噪声。 所得到的滤波信号可以与输入的数字信号与测试信号发生器进行比较，以确定ADC的传输特性。
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公开(公告)号：US10484004B2
公开(公告)日：2019-11-19
申请号：US16151404
申请日：2018-10-04
Applicant: MEDIATEK Inc.
Inventor： Tien-Yu Lo
IPC: H03M3/00
Abstract: A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.
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公开(公告)号：US20190199368A1
公开(公告)日：2019-06-27
申请号：US16190168
申请日：2018-11-14
Applicant: MEDIATEK INC.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
IPC: H03M3/00
CPC classification number: H03M3/424 , H03M1/06 , H03M1/10 , H03M1/12 , H03M3/30 , H03M3/426 , H03M3/454 , H03M3/456 , H03M3/464
Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.
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Patent Agency Ranking
公开(公告)号：US20170353191A1
公开(公告)日：2017-12-07
申请号：US15586332
申请日：2017-05-04
Applicant: MEDIATEK Inc.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
IPC: H03M3/00
Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.
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公开(公告)号：US20200295776A1
公开(公告)日：2020-09-17
申请号：US16809535
申请日：2020-03-04
Applicant: MEDIATEK INC.
Inventor： Tien-Yu Lo , Chan-Hsiang Weng , Su-Hao Wu
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.
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公开(公告)号：US10432214B2
公开(公告)日：2019-10-01
申请号：US16190168
申请日：2018-11-14
Applicant: MEDIATEK INC.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.
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公开(公告)号：US10141948B2
公开(公告)日：2018-11-27
申请号：US15586332
申请日：2017-05-04
Applicant: MEDIATEK Inc.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
IPC: H03M3/00
Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.
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公开(公告)号：US10979069B2
公开(公告)日：2021-04-13
申请号：US16809535
申请日：2020-03-04
Applicant: MEDIATEK INC.
Inventor： Tien-Yu Lo , Chan-Hsiang Weng , Su-Hao Wu
Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.
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