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    Integrated circuit (IC) package with integrated inductor having core magnetic field (B field) extending parallel to substrate
    1.
    发明授权
    Integrated circuit (IC) package with integrated inductor having core magnetic field (B field) extending parallel to substrate 有权

    公开(公告)号：US11723222B2

    公开(公告)日：2023-08-08

    申请号：US17074848

    申请日：2020-10-20

    Applicant: Microchip Technology Incorporated

    Inventor： Yaojian Leng ,  Justin Sato ,  Bomy Chen

    IPC: H10K19/00 ,  H10K19/10 ,  H01L49/02

    CPC classification number: H10K19/201 ,  H10K19/10 ,  H01L28/10

    Abstract: An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

    INTEGRATED CIRCUIT PACKAGE MODULE INCLUDING A BONDING SYSTEM
    2.
    发明申请
    INTEGRATED CIRCUIT PACKAGE MODULE INCLUDING A BONDING SYSTEM 有权

    公开(公告)号：US20230099856A1

    公开(公告)日：2023-03-30

    申请号：US17665749

    申请日：2022-02-07

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Julius Kovats

    IPC: H01L23/498 ,  H01L23/50 ,  H01L25/065

    Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

    Mixed-orientation multi-die integrated circuit package with at least one vertically-mounted die
    4.
    发明授权
    Mixed-orientation multi-die integrated circuit package with at least one vertically-mounted die 有权

    公开(公告)号：US11043471B2

    公开(公告)日：2021-06-22

    申请号：US16540117

    申请日：2019-08-14

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Sato ,  Bomy Chen

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

    Abstract: A mixed-orientation multi-die (“MOMD”) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base. MOMD packages may provide a reduced lateral footprint and increased die integration per unit area, as compared with conventional multi-die packages.

    EEPROM memory cell with low voltage read path and high voltage erase/write path
    6.
    发明授权
    EEPROM memory cell with low voltage read path and high voltage erase/write path 有权
    具有低电压读取通道和高电压擦除/写入通道的EEPROM存储单元

    公开(公告)号：US09455037B2

    公开(公告)日：2016-09-27

    申请号：US14209275

    申请日：2014-03-13

    Applicant: Microchip Technology Incorporated

    Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

    IPC: G11C11/34 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

    CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

    Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

    Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。

    Sidewall type memory cell
    7.
    发明授权
    Sidewall type memory cell 有权
    侧壁式存储单元

    公开(公告)号：US09444040B2

    公开(公告)日：2016-09-13

    申请号：US14183831

    申请日：2014-02-19

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Hiroki Sato ,  Bomy Chen ,  Sonu Daryanani

    IPC: H01L47/00 ,  H01L45/00

    CPC classification number: H01L45/1226 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/1675

    Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

    Abstract translation: 侧壁型存储单元（例如，CBRAM，ReRAM或PCM单元）可以包括底部电极，限定侧壁的顶部电极层和布置在底部和顶部电极层之间的电解质层，使得导电路径 经由电解质层限定在底部电极和顶部电极侧壁之间，其中底部电极层相对于水平衬底大致水平地延伸，并且顶部电极侧壁相对于水平衬底非水平地延伸，使得 当向单元施加正偏置电压时，导电路径在底电极和顶电极侧壁之间的非垂直方向（例如大致水平方向或其它非垂直方向）上生长。

    High Voltage Double-Diffused MOS (DMOS) Device and Method of Manufacture
    8.
    发明申请
    High Voltage Double-Diffused MOS (DMOS) Device and Method of Manufacture 有权
    高电压双扩散MOS（DMOS）器件及其制造方法

    公开(公告)号：US20150200198A1

    公开(公告)日：2015-07-16

    申请号：US14157337

    申请日：2014-01-16

    Applicant: Microchip Technology Incorporated

    Inventor： Bomy Chen ,  Sonu Daryanani

    IPC: H01L27/115 ,  H01L29/66 ,  H01L23/552 ,  H01L29/78

    CPC classification number: H01L29/7816 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/2652 ,  H01L21/266 ,  H01L23/552 ,  H01L27/11524 ,  H01L27/11543 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7801 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

    Abstract translation: 形成集成的DMOS晶体管/ EEPROM单元的方法包括在衬底上形成第一掩模，使用第一掩模在衬底中形成漂移注入以对准漂移注入，同时在漂移注入上形成第一浮栅，以及 与所述漂移注入件间隔开的第二浮动栅极，形成覆盖所述第二浮动栅极并覆盖所述第一浮动栅极的一部分的第二掩模，使用所述第一浮动栅极的边缘在所述基板中形成基底注入以使所述基底 并且同时在第一浮动栅极上形成第一控制栅极，并且在第二浮栅上方形成第二控制栅极。 第一浮栅，第一控制栅，漂移注入和基极注入形成DMOS晶体管的组件，第二浮栅和第二控制栅形成EEPROM单元的组件。

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