-
公开(公告)号：US20230024167A1
公开(公告)日：2023-01-26
申请号：US17590650
申请日：2022-02-01
发明人： Eric N. Lee , Dheeraj Srinivasan
IPC分类号： G06F3/06
摘要： A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.
-
公开(公告)号：US20220208273A1
公开(公告)日：2022-06-30
申请号：US17382619
申请日：2021-07-22
摘要： Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.
-
公开(公告)号：US10936210B2
公开(公告)日：2021-03-02
申请号：US16506020
申请日：2019-07-09
IPC分类号： G06F3/06 , G06F12/0811
摘要： The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
-
公开(公告)号：US20210057031A1
公开(公告)日：2021-02-25
申请号：US17090067
申请日：2020-11-05
摘要： The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.
-
公开(公告)号：US20230059543A1
公开(公告)日：2023-02-23
申请号：US17887940
申请日：2022-08-15
发明人： Andrea Giovanni Xotta , Dheeraj Srinivasan , Ali Mohammadzadeh , Karl D. Schuh , Guido Luciano Rizzo , Jung Sheng Hoei , Michele Piccardi , Tommaso Vali , Umberto Siciliani , Rohitkumar Makhija , June Lee , Aaron S. Yip , Daniel J. Hubbard
IPC分类号： G06F3/06
摘要： A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.
-
公开(公告)号：US11562791B1
公开(公告)日：2023-01-24
申请号：US17396825
申请日：2021-08-09
发明人： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
摘要： Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.
-
公开(公告)号：US11276470B2
公开(公告)日：2022-03-15
申请号：US16947091
申请日：2020-07-17
摘要： A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and one or more bitline driver circuits coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The one or more bitline driver circuits can perform a first pre-charging operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.
-
公开(公告)号：US20210181955A1
公开(公告)日：2021-06-17
申请号：US17187066
申请日：2021-02-26
IPC分类号： G06F3/06 , G06F12/0811
摘要： The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
-
公开(公告)号：US10977186B2
公开(公告)日：2021-04-13
申请号：US15819941
申请日：2017-11-21
IPC分类号： G06F12/02 , G06F3/06 , G06F12/1009 , G11C11/56 , G06F11/07
摘要： An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.
-
公开(公告)号：US10372353B2
公开(公告)日：2019-08-06
申请号：US15609569
申请日：2017-05-31
IPC分类号： G06F12/00 , G06F13/00 , G06F3/06 , G06F12/0811
摘要： The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
-
-
-
-
-
-
-
-
-
搜索结果
40 条记录 (耗时 0.021 秒)