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公开(公告)号：US11847335B2
公开(公告)日：2023-12-19
申请号：US17212437
申请日：2021-03-25
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Scott Anthony Stoller , Niccolo' Righetti , Giuseppina Puzzilli
IPC: G06F3/06
CPC classification number: G06F3/0647 , G06F3/0604 , G06F3/0625 , G06F3/0679
Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.
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公开(公告)号：US11776629B2
公开(公告)日：2023-10-03
申请号：US16995517
申请日：2020-08-17
Applicant: Micron Technology, Inc.
Inventor： Niccolo' Righetti , Kishore K. Muchherla , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage.
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公开(公告)号：US20220197536A1
公开(公告)日：2022-06-23
申请号：US17127373
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Priya Venkataraman , Pitamber Shukla , Scott A. Stoller , Giuseppina Puzzilli , Niccolo' Righetti
IPC: G06F3/06
Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.
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公开(公告)号：US20210200461A1
公开(公告)日：2021-07-01
申请号：US17079048
申请日：2020-10-23
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Mark A. Helm , Giuseppina Puzzilli , Peter Feeley , Yifen Liu , Violante Moschiano , Akira Goda , Sampath K. Ratnam
IPC: G06F3/06
Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
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公开(公告)号：US11899966B2
公开(公告)日：2024-02-13
申请号：US17872206
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Mark A. Helm , Giuseppina Puzzilli , Peter Feeley , Yifen Liu , Violante Moschiano , Akira Goda , Sampath K. Ratnam
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0644 , G06F3/0679
Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
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Patent Agency Ranking
公开(公告)号：US11709616B2
公开(公告)日：2023-07-25
申请号：US17890885
申请日：2022-08-18
Applicant: Micron Technology, Inc.
Inventor： Priya Venkataraman , Pitamber Shukla , Scott A. Stoller , Giuseppina Puzzilli , Niccolo′ Righetti
IPC: G06F3/06
CPC classification number: G06F3/0652 , G06F3/0625 , G06F3/0679
Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.
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公开(公告)号：US11694763B2
公开(公告)日：2023-07-04
申请号：US17700085
申请日：2022-03-21
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
CPC classification number: G11C29/44 , G06F11/076 , G06F11/0772 , G06F11/3037 , G11C29/12005 , G11C29/42
Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
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公开(公告)号：US20220391125A1
公开(公告)日：2022-12-08
申请号：US17890885
申请日：2022-08-18
Applicant: Micron Technology, Inc.
Inventor： Priya Venkataraman , Pitamber Shukla , Scott A. Stoller , Giuseppina Puzzilli , Niccolo' Righetti
IPC: G06F3/06
Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.
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公开(公告)号：US11481273B2
公开(公告)日：2022-10-25
申请号：US16995359
申请日：2020-08-17
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo′ Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.
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公开(公告)号：US20220291865A1
公开(公告)日：2022-09-15
申请号：US17829861
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.
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