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    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    2.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20230062084A1

    公开(公告)日：2023-03-02

    申请号：US17475057

    申请日：2021-09-14

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Haoyu Li

    IPC: H01L27/11582 ,  H01L27/11556

    Abstract: A memory array comprising strings of memory cells comprises conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprising a vertical stack comprises alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. Other embodiments, including method, are disclosed.

    APPARATUSES INCLUDING LAMINATE SPACER STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS
    7.
    发明申请
    APPARATUSES INCLUDING LAMINATE SPACER STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS 审中-公开

    公开(公告)号：US20200373304A1

    公开(公告)日：2020-11-26

    申请号：US16420429

    申请日：2019-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Silvia Borsari ,  Stian E. Wood ,  Haoyu Li ,  Yiping Wang

    IPC: H01L27/108

    Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

    Integrated assemblies and methods of forming integrated assemblies
    8.
    发明授权
    Integrated assemblies and methods of forming integrated assemblies 有权

    公开(公告)号：US10354989B1

    公开(公告)日：2019-07-16

    申请号：US15980908

    申请日：2018-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

    IPC: G11C11/34 ,  H01L27/02 ,  H01L23/532 ,  G11C5/06 ,  H01L27/12 ,  H01L21/82

    Abstract: An integrated assembly having an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Also, an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Also, methods of forming integrated assemblies.

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