公开(公告)号：US20230164985A1

公开(公告)日：2023-05-25

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US11469103B2

公开(公告)日：2022-10-11

申请号：US17153997

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

公开(公告)号：US11387369B2

公开(公告)日：2022-07-12

申请号：US16723259

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Shen Hu ,  Hung-Wei Liu ,  Xiao Li ,  Zhiqiang Xie ,  Corey Staller ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Thomas A. Figura

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

公开(公告)号：US11322388B2

公开(公告)日：2022-05-03

申请号：US16549594

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Shen Hu ,  Kangle Li ,  Sanjeev Sapra

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/67 ,  H01L21/02

Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.

公开(公告)号：US20210193843A1

公开(公告)日：2021-06-24

申请号：US16723259

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Shen Hu ,  Hung-Wei Liu ,  Xiao Li ,  Zhiqiang Xie ,  Corey Staller ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Thomas A. Figura

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

公开(公告)号：US20220102351A1

公开(公告)日：2022-03-31

申请号：US17643316

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: H01L27/108 ,  G11C11/408

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US20210143011A1

公开(公告)日：2021-05-13

申请号：US17153997

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

IPC: H01L21/02 ,  H01L21/762

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

公开(公告)号：US20210202487A1

公开(公告)日：2021-07-01

申请号：US16729076

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: H01L27/108 ,  G11C11/408

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US12295140B2

公开(公告)日：2025-05-06

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US11925014B2

公开(公告)日：2024-03-05

申请号：US17643316

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: G11C11/24 ,  G11C11/408 ,  H10B12/00

CPC classification number: H10B12/312 ,  G11C11/4087 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.