公开(公告)号：US12153490B2

公开(公告)日：2024-11-26

申请号：US17566921

申请日：2021-12-31

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Vipul Patel ,  Scott A. Stoller

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G06F12/0882 ,  G11C29/04 ,  G11C29/44

Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

公开(公告)号：US20240061616A1

公开(公告)日：2024-02-22

申请号：US18227642

申请日：2023-07-28

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/0679

Abstract: A memory device including control logic to identify a command issued to the memory device to execute a memory access operation on one or more memory cells of a memory array of the memory device. The control logic determines a command type associated with the command and identifies, based on the command type, a subset of target information to be stored as part of a set of command information. The control logic stores, in a data store of the memory device, the set of command information associated with the command.

公开(公告)号：US11763897B2

公开(公告)日：2023-09-19

申请号：US17864041

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Vipul Patel

IPC: G11C5/14 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

公开(公告)号：US20200319796A1

公开(公告)日：2020-10-08

申请号：US16374188

申请日：2019-04-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vipul Patel

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: A memory includes a memory array comprising a plurality of pages, a page buffer, and search logic. The page buffer includes first registers, second registers, compare logic, and third registers. The first registers store data read from a page of the memory array. The second registers store a user pattern. The compare logic compares the data stored in the first registers to the user pattern stored in the second registers. The third registers store the comparison results. The search logic is configured to identify addresses of the memory array where the comparison results stored in the third registers indicate a match between the data read from the page and column of the memory array and the user pattern. The first registers are loaded with data from a following page of the memory array concurrently with the search logic identifying addresses indicating a match in a previous page of the memory array.

公开(公告)号：US10692580B2

公开(公告)日：2020-06-23

申请号：US16274806

申请日：2019-02-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vipul Patel

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/28 ,  G11C11/56

Abstract: Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number of memory cells of a subset of memory cells of the particular grouping of memory cells having a particular data state, and, if the number of memory cells of the subset of memory cells having the particular data state is less than a particular threshold, adjusting a voltage level of the read voltage in response to the number of memory cells of the subset of memory cells having the particular data state and reading the particular grouping of memory cells using the read voltage having the adjusted voltage level.

公开(公告)号：US11669139B2

公开(公告)日：2023-06-06

申请号：US17472862

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel

IPC: G06F1/28 ,  G06F1/3296 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3234

CPC classification number: G06F1/28 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0683

Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.

公开(公告)号：US20220415410A1

公开(公告)日：2022-12-29

申请号：US17864041

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Vipul Patel

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

公开(公告)号：US20190206499A1

公开(公告)日：2019-07-04

申请号：US16274806

申请日：2019-02-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vipul Patel

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30

Abstract: Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number of memory cells of a subset of memory cells of the particular grouping of memory cells having a particular data state, and, if the number of memory cells of the subset of memory cells having the particular data state is less than a particular threshold, adjusting a voltage level of the read voltage in response to the number of memory cells of the subset of memory cells having the particular data state and reading the particular grouping of memory cells using the read voltage having the adjusted voltage level.

公开(公告)号：US20220319612A1

公开(公告)日：2022-10-06

申请号：US17845785

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Vipul Patel ,  Theodore Pekny

IPC: G11C16/22 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.

公开(公告)号：US20220108755A1

公开(公告)日：2022-04-07

申请号：US17065359

申请日：2020-10-07

Applicant: Micron Technology, Inc.

Inventor： Ezra E. Hartz ,  Vipul Patel

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.