公开(公告)号：US10223197B2

公开(公告)日：2019-03-05

申请号：US14820436

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Nur Engin ,  Steven Thoen ,  Jose Pineda de Gyvez

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/35

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

公开(公告)号：US09917588B2

公开(公告)日：2018-03-13

申请号：US14794411

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Kristof Blutman ,  Ajay Kapoor ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03L5/00 ,  H03K19/0185 ,  H03K5/13

CPC classification number: H03K19/018514 ,  H03K3/356182 ,  H03K5/13 ,  H03K19/0185

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

公开(公告)号：US09912335B2

公开(公告)日：2018-03-06

申请号：US14794485

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03L5/00 ,  H03K19/0185 ,  G06F1/32 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/018507 ,  G06F1/3234 ,  H03K19/0019 ,  H03K19/0175

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

公开(公告)号：US20170012627A1

公开(公告)日：2017-01-12

申请号：US14794485

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03K19/0185

CPC classification number: H03K19/018507 ,  G06F1/3234 ,  H03K19/0019 ,  H03K19/0175

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

Abstract translation: 本公开的方面涉及通过各个电路之间的通信的电平转换方法。 如可以根据本文特征的一个或多个实施例来实现的，在各个电路之间通过的通信的电压电平被选择性地移位。 在各个电路在相对于彼此在电压范围内移位的相应功率域下工作时，通信的电压电平发生偏移。 例如，该方法可以有助于对于其中提供一个电路的低电平电压作为另一个电路的高电平电压的堆叠电路的功率节省。 当各个电路在公共功率域下工作时，通信直接在相应的电路之间传递（例如，绕过任何电平转换，并促进快速通信）。

公开(公告)号：US09065439B2

公开(公告)日：2015-06-23

申请号：US14168910

申请日：2014-01-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Rinze Ida Mechtildis Pete Meijer ,  Jose Pineda de Gyvez

IPC: H03K19/0185 ,  H03K19/00 ,  G06F1/10 ,  H03K19/0175

CPC classification number: H03K19/0016 ,  G06F1/10 ,  H03K19/017581 ,  H03K19/018521

Abstract: A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.

Abstract translation: 在时钟树中使用的可调谐缓冲电路具有并联的多个缓冲器，每个缓冲器具有接地功能，以及与缓冲器并联的旁路开关。 该电路具有连接到电路中的一个缓冲器的正常模式，多个缓冲器的第一低电压模式并联连接而不具有接地功能，缓冲器的第二低电压模式并联到接地功能和旁路模式 。

公开(公告)号：US20140258686A1

公开(公告)日：2014-09-11

申请号：US14195657

申请日：2014-03-03

Applicant: NXP B.V.

Inventor： Hamed Fatemi ,  Jose Pineda de Gyvez ,  Juan Echeverri Escobar

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality of instructions and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies. The integrated circuit is operable in a first power mode and a second power mode. The second power mode is a reduced power mode compared to the first power mode and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies.

Abstract translation: 一种集成电路，包括一组数据处理单元，包括第一数据处理单元和至少一个以可变频率工作的第二数据处理单元。 集成电路还包括指令调度器，其适于评估接收的多个指令中的各个指令之间的数据依赖性，并且将指令分配给第一数据处理单元和至少一个第二数据处理单元，用于根据所述数据依赖性进行并行执行 。 集成电路可在第一功率模式和第二功率模式下操作。 第二功率模式是与第一功率模式相比的降低功率模式，并且适于根据评估数据调整第二数据处理单元和第二功率模式中的至少一个第二数据处理单元的工作频率 依赖关系。

公开(公告)号：US20170039104A1

公开(公告)日：2017-02-09

申请号：US14820436

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Nur Engin ,  Steven Thoen ,  Jose Pineda de Gyvez

IPC: G06F11/10 ,  H03M13/35 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/353

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract translation: 根据本发明的一个实施例，公开了一种集成电路（IC）装置。 在该实施例中，IC器件包括SRAM模块，耦合到SRAM模块的封装逻辑，上下文源以及耦合到上下文源和封装逻辑的ECC简档控制器，ECC简档控制器被配置为选择ECC简档 响应于从上下文源接收的用于由包装器逻辑使用的上下文信息。

公开(公告)号：US20170012628A1

公开(公告)日：2017-01-12

申请号：US14794411

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Kristof Blutman ,  Ajay Kapoor ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03K19/0185

CPC classification number: H03K19/018514 ,  H03K3/356182 ,  H03K5/13 ,  H03K19/0185

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract translation: 本公开的方面涉及可以在每个域在不同电压范围上操作的堆叠布置中操作的相应功率域（电路）之间的通信。 第一电路提供基于从第一功率域接收的输入信号的转变而在第一和第二电压电平之间变化的差分输出。 第一和第二驱动器电路分别耦合到第一和第二差分输出。 第三驱动器电路与第一和第二电路一起工作，以响应于输入信号处于第二电压电平，通过驱动处于第二电压电平的输出电路来将输入信号从第一功率域电平移位到第二电源域上的输出信号 第一电压电平，并且响应于输入信号处于第二电压电平，将输出电路驱动在第三电压电平。

公开(公告)号：US09465614B2

公开(公告)日：2016-10-11

申请号：US14195657

申请日：2014-03-03

Applicant: NXP B.V.

Inventor： Hamed Fatemi ,  Jose Pineda de Gyvez ,  Juan Echeverri Escobar

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality of instructions and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies. The integrated circuit is operable in a first power mode and a second power mode. The second power mode is a reduced power mode compared to the first power mode and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies.

Abstract translation: 一种集成电路，包括一组数据处理单元，包括第一数据处理单元和至少一个以可变频率工作的第二数据处理单元。 集成电路还包括指令调度器，其适于评估接收的多个指令中的各个指令之间的数据依赖性，并且将指令分配给第一数据处理单元和至少一个第二数据处理单元，用于根据所述数据依赖性进行并行执行 。 集成电路可在第一功率模式和第二功率模式下操作。 第二功率模式是与第一功率模式相比的降低功率模式，并且适于根据评估数据调整第二数据处理单元和第二功率模式中的至少一个第二数据处理单元的工作频率 依赖关系。

公开(公告)号：US20140225645A1

公开(公告)日：2014-08-14

申请号：US14168910

申请日：2014-01-30

Applicant: NXP B.V.

Inventor： Vibhu SHARMA ,  Rinze Ida Mechtildis Pete MEIJER ,  Jose Pineda de Gyvez

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  G06F1/10 ,  H03K19/017581 ,  H03K19/018521

Abstract: A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.

Abstract translation: 在时钟树中使用的可调谐缓冲电路具有并联的多个缓冲器，每个缓冲器具有接地功能，以及与缓冲器并联的旁路开关。 该电路具有连接到电路中的一个缓冲器的正常模式，多个缓冲器的第一低电压模式并联连接而不具有接地功能，缓冲器的第二低电压模式并联到接地功能和旁路模式 。