公开(公告)号：US07759744B2

公开(公告)日：2010-07-20

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62 ,  H01L27/10 ,  H01L29/73

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，在硅衬底102上包括第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数膜的P型MOSFET 120 12和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。第一 高介电常数膜111和第二高介电常数膜112含有选自Hf和Zr的一种或多种元素。

公开(公告)号：US20050253181A1

公开(公告)日：2005-11-17

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L31/119

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数的P型MOSFET 120 膜112和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。 第一高介电常数膜111和第二高介电常数膜112包含从由Hf和Zr组成的组中选择的一种或多种元素。

公开(公告)号：US20050263802A1

公开(公告)日：2005-12-01

申请号：US11129439

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。 低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。 包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

公开(公告)号：US07238996B2

公开(公告)日：2007-07-03

申请号：US11129439

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

IPC分类号： H01L29/70

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。 低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。 包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

公开(公告)号：US08787067B2

公开(公告)日：2014-07-22

申请号：US13359449

申请日：2012-01-26

申请人： Motofumi Saitoh ,  Masayuki Terai

发明人： Motofumi Saitoh ,  Masayuki Terai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/145

摘要： Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.

摘要翻译： 提供一种半导体器件，包括：具有可变电阻器件的存储单元; 以及控制单元，其控制施加到所述存储单元的电压，其中所述可变电阻装置包括下电极，所述下电极包含第一金属材料，包含第二金属材料的上电极和含氧的绝缘膜，所述第一金属材料具有 归一化的氧化物形成能量高于第二金属材料，并且控制单元在增加绝缘膜的电阻值的操作时向上部电极施加正电压，并且降低其电阻值的操作 并且在读出绝缘膜的电阻值的操作时向下电极施加正电压。

公开(公告)号：US07838945B2

公开(公告)日：2010-11-23

申请号：US12093666

申请日：2006-10-18

申请人： Motofumi Saitoh ,  Hirohito Watanabe

发明人： Motofumi Saitoh ,  Hirohito Watanabe

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

摘要翻译： 半导体器件包括半导体衬底上的第一和第二有源区，由元件隔离区隔开; 线状电极，其经由元件隔离区域从第一至第二有源区域上方设置; 第一和第二FET分别包括在第一和第二有源区上的栅极绝缘膜，由线状电极和源极/漏极区组成的栅电极。 第一和第二活性区域上的线状电极的部分由不同的材料形成。 线状电极包括扩散抑制区域，该扩散抑制区域在垂直于衬底的方向上的厚度小于第一和第二有源区域上的厚度。 扩散抑制区域在元件隔离区域的上方，并且跨越栅极长度方向的线状电极的整个宽度。

公开(公告)号：US20090096032A1

公开(公告)日：2009-04-16

申请号：US12093666

申请日：2006-10-18

申请人： Motofumi Saitoh ,  Hirohito Watanabe

发明人： Motofumi Saitoh ,  Hirohito Watanabe

IPC分类号： H01L27/092 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

摘要翻译： 半导体器件包括半导体衬底上的第一和第二有源区，由元件隔离区隔开; 线状电极，其经由元件隔离区域从第一至第二有源区域上方设置; 第一和第二FET分别包括在第一和第二有源区上的栅极绝缘膜，由线状电极和源极/漏极区组成的栅电极。 第一和第二活性区域上的线状电极的部分由不同的材料形成。 线状电极包括扩散抑制区域，该扩散抑制区域在垂直于衬底的方向上的厚度小于第一和第二有源区域上的厚度。 扩散抑制区域在元件隔离区域的上方，并且跨越栅极长度方向的线状电极的整个宽度。

公开(公告)号：US20110311178A1

公开(公告)日：2011-12-22

申请号：US13202680

申请日：2010-02-18

申请人： Junichi Fujikata ,  Jun Ushida ,  Akio Toda ,  Motofumi Saitoh

发明人： Junichi Fujikata ,  Jun Ushida ,  Akio Toda ,  Motofumi Saitoh

IPC分类号： G02F1/025

CPC分类号： G02F1/025

摘要： The components are a lower clad layer (102), a first silicon layer (103) that is formed on the lower clad layer (102) as a single body made of silicon of a first conduction type and has a slab region (105) that is disposed at a core (104) and on both sides of the core (104) and connects to the core, a concave section (104a) that is formed in the top surface of the core (104), and a second silicon layer (109) of a second conduction type that is formed inside the concave section (104a) with an intervening dielectric layer (108) to fill the inside of the concave section (104a).

摘要翻译： 这些部件是下包层（102），第一硅层（103），其形成在下包层（102）上，作为由第一导电类型的硅制成的单体，并具有板区域（105） 设置在芯部（104）处并且在芯部（104）的两侧并且连接到芯部，形成在芯部（104）的顶表面中的凹部（104a）和第二硅层（ 109），其形成在所述凹部（104a）的内部，并具有填充所述凹部（104a）的内部的中间介电层（108）。

公开(公告)号：US20130064491A1

公开(公告)日：2013-03-14

申请号：US13582841

申请日：2011-03-01

申请人： Junichi Fujikata ,  Motofumi Saitoh ,  Jun Ushida ,  Akio Toda

发明人： Junichi Fujikata ,  Motofumi Saitoh ,  Jun Ushida ,  Akio Toda

IPC分类号： G02F1/035 ,  H01L21/02

CPC分类号： G02F1/035 ,  G02F1/025 ,  H01L21/02

摘要： To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.

摘要翻译： 提供具有减小的尺寸和降低的功率消耗并且能够容易地连接到波导的光学调制器和制造光学调制器的方法。 光调制器至少具有肋状部分并掺杂成第一导电类型的半导体层（8），布置在第一导电型半导体层（8）上的电介质层（11）和半导体层 放置在电介质层（11）上的与介电层（11）相对的宽度相对于肋状部分的宽度增加并且掺杂成第二导电类型的放电层（9）。

公开(公告)号：US08873895B2

公开(公告)日：2014-10-28

申请号：US13582841

申请日：2011-03-01

申请人： Junichi Fujikata ,  Motofumi Saitoh ,  Jun Ushida ,  Akio Toda

发明人： Junichi Fujikata ,  Motofumi Saitoh ,  Jun Ushida ,  Akio Toda

IPC分类号： G02F1/035 ,  H01L21/02

CPC分类号： G02F1/035 ,  G02F1/025 ,  H01L21/02

摘要： To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.

摘要翻译： 提供具有减小的尺寸和降低的功率消耗并且能够容易地连接到波导的光学调制器和制造光学调制器的方法。 光调制器至少具有肋状部分并掺杂成第一导电类型的半导体层（8），布置在第一导电型半导体层（8）上的电介质层（11）和半导体层 放置在电介质层（11）上的与介电层（11）相对的宽度相对于肋状部分的宽度增加并且掺杂成第二导电类型的放电层（9）。