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1.发明授权公开(公告)号：US10432879B2
公开(公告)日：2019-10-01
申请号：US15872741
申请日：2018-01-16
Applicant: OmniVision Technologies, Inc.
Inventor： Chun-Hsiang Chang , Yingkan Lin , Jingwei Lai , Zhe Gao
Abstract: A readout circuit includes a comparator coupled to receive a ramp signal an output of a dual conversion gain pixel. A single counter is coupled to the output of the comparator. The counter is coupled to write to only one of a first or a second memory circuits at a time. A first multiplexor is coupled to load either an initial value or an initial memory value from the first memory circuit into the counter. A second multiplexor is coupled to load either a low conversion gain memory value from the first memory circuit or a high conversion gain memory value from the second memory circuit into a single data transmitter, which is coupled to transmit the received memory value to a digital processor.
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2.发明申请公开(公告)号：US20190222780A1
公开(公告)日：2019-07-18
申请号：US15872741
申请日：2018-01-16
Applicant: OmniVision Technologies, Inc.
Inventor： Chun-Hsiang Chang , Yingkan Lin , Jingwei Lai , Zhe Gao
CPC classification number: H04N5/355 , H04N5/2355 , H04N5/3559 , H04N5/37452 , H04N5/378
Abstract: A readout circuit includes a comparator coupled to receive a ramp signal an output of a dual conversion gain pixel. A single counter is coupled to the output of the comparator. The counter is coupled to write to only one of a first or a second memory circuits at a time. A first multiplexor is coupled to load either an initial value or an initial memory value from the first memory circuit into the counter. A second multiplexor is coupled to load either a low conversion gain memory value from the first memory circuit or a high conversion gain memory value from the second memory circuit into a single data transmitter, which is coupled to transmit the received memory value to a digital processor.
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公开(公告)号：US20230179889A1
公开(公告)日：2023-06-08
申请号：US17540434
申请日：2021-12-02
Applicant: OmniVision Technologies,Inc.
Inventor： Chao-Fang Tsai , Zheng Yang , Chun-Hsiang Chang
IPC: H04N5/3745 , H03M1/46 , H03M1/56 , H04N5/378
CPC classification number: H04N5/37455 , H03M1/468 , H03M1/462 , H03M1/56 , H04N5/378
Abstract: A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.
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公开(公告)号：US09876979B1
公开(公告)日：2018-01-23
申请号：US15371009
申请日：2016-12-06
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chun-Hsiang Chang , Yu-Shen Yang , Yingkan Lin , Liping Deng
CPC classification number: H04N5/378 , G05F1/575 , H01L27/14643 , H03B5/1271 , H03B5/366 , H03B2201/0275 , H04N5/374 , H04N5/953
Abstract: An example current generator may include a low dropout regulator (LDO) coupled to receive a reference voltage and provide a reference current in response, where the LDO adjusts a current level of the current reference in response to a calibration signal. A current controlled oscillator coupled to receive a reference current copy from the LDO and generate an oscillating signal in response, where a period of the oscillating signal is based at least in part on a level of the reference current copy. A pulse generator coupled to provide an adjustable pulse signal. A counter coupled to determine a number of periods of the oscillating signal occurring during a duration of the pulse signal, and provide a control signal indicative of such, and a digital calibration circuit coupled to receive the control signal and provide the calibration signal to the LDO in response.
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Patent Agency Ranking
公开(公告)号：US11659302B1
公开(公告)日：2023-05-23
申请号：US17540434
申请日：2021-12-02
Applicant: OmniVision Technologies,Inc.
Inventor： Chao-Fang Tsai , Zheng Yang , Chun-Hsiang Chang
IPC: H04N25/772 , H03M1/46 , H03M1/56 , H04N25/75 , H03M1/12
CPC classification number: H04N25/772 , H03M1/462 , H03M1/468 , H03M1/56 , H04N25/75
Abstract: A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.
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公开(公告)号：US20210368116A1
公开(公告)日：2021-11-25
申请号：US16882254
申请日：2020-05-22
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chun-Hsiang Chang , Zejian Wang , Chao-Fang Tsai , Jingwei Lai
Abstract: A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.
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公开(公告)号：US11632512B2
公开(公告)日：2023-04-18
申请号：US17180520
申请日：2021-02-19
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Lihang Fan , Min Qu , Chao-Fang Tsai , Chun-Hsiang Chang
Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.
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公开(公告)号：US20220269482A1
公开(公告)日：2022-08-25
申请号：US17180520
申请日：2021-02-19
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Lihang Fan , Min Qu , Chao-Fang Tsai , Chun-Hsiang Chang
Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.
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公开(公告)号：US11206368B2
公开(公告)日：2021-12-21
申请号：US16882254
申请日：2020-05-22
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chun-Hsiang Chang , Zejian Wang , Chao-Fang Tsai , Jingwei Lai
Abstract: A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.
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