Carrier and component with a buffer layer, and method for producing a component

    公开(公告)号:US11450794B2

    公开(公告)日:2022-09-20

    申请号:US16639722

    申请日:2018-07-23

    Abstract: A carrier and a component are disclosed. In an embodiment a component includes a semiconductor chip including a substrate and a semiconductor body arranged thereon and a metallic carrier having a coefficient of thermal expansion which is at least 1.5 times greater than a coefficient of thermal expansion of the substrate or of the semiconductor chip, wherein the semiconductor chip is attached to a mounting surface of the metallic carrier by a connection layer such that the connection layer is located between the semiconductor chip and a buffer layer and adjoins a rear side of the semiconductor chip, wherein the buffer layer has a yield stress which is at least 10 MPa and at most 300 MPa, and wherein the substrate of the semiconductor chip and the metallic carrier of the component have a higher yield stress than the buffer layer.

    Carrier and Component with a Buffer Layer, and Method for Producing a Component

    公开(公告)号:US20200235271A1

    公开(公告)日:2020-07-23

    申请号:US16639722

    申请日:2018-07-23

    Abstract: A carrier and a component are disclosed. In an embodiment a component includes a semiconductor chip including a substrate and a semiconductor body arranged thereon and a metallic carrier having a coefficient of thermal expansion which is at least 1.5 times greater than a coefficient of thermal expansion of the substrate or of the semiconductor chip, wherein the semiconductor chip is attached to a mounting surface of the metallic carrier by a connection layer such that the connection layer is located between the semiconductor chip and a buffer layer and adjoins a rear side of the semiconductor chip, wherein the buffer layer has a yield stress which is at least 10 MPa and at most 300 MPa, and wherein the substrate of the semiconductor chip and the metallic carrier of the component have a higher yield stress than the buffer layer.

    Optoelectronic component and the connectivity thereof

    公开(公告)号:US12057539B2

    公开(公告)日:2024-08-06

    申请号:US17055040

    申请日:2019-04-02

    CPC classification number: H01L33/62 H01L25/167 H01L33/486

    Abstract: The invention relates to an optoelectronic component having: a carrier; an optoelectronic semiconductor chip; an insulation layer, which has an electrically insulating material; and a first contact layer, which has an electrically conductive material. According to the invention, the insulation layer is arranged on the carrier and has a cavity; the semiconductor chip is arranged in the cavity; the first contact layer is arranged between the semiconductor chip and the carrier and between the insulation layer and the carrier; and the first contact layer has at least one interruption, such that the carrier is free of the first contact layer at least in some parts in the region of the cavity.

    COMPONENT HAVING A BUFFER LAYER AND METHOD FOR PRODUCING A COMPONENT

    公开(公告)号:US20200227604A1

    公开(公告)日:2020-07-16

    申请号:US16640062

    申请日:2018-07-19

    Abstract: A component may include a semiconductor chip, a buffer layer, a connecting layer, and a metal carrier. The semiconductor chip may include a substrate and a semiconductor body arranged thereon. The metal carrier may have a thermal expansion coefficient at least 1.5 times as great as a thermal expansion coefficient of the substrate or of the semiconductor chip. The chip may be fastened on the metal carrier by the connecting layer, and the buffer layer may have a yield stress ranging from 10 MPa. The buffer layer may have a thickness ranging from 2 um to 10 um and adjoin the chip. The substrate and the metal carrier may have a higher yield strength than the buffer layer.

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