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    Apparatus and process for sampling a serial digital signal
    1.
    发明授权
    Apparatus and process for sampling a serial digital signal 失效
    串行数字信号采样的装置和处理

    公开(公告)号：US5848109A

    公开(公告)日：1998-12-08

    申请号：US510458

    申请日：1995-08-02

    Applicant: Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

    Inventor： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

    IPC: H04L7/00 ,  H04L7/033 ,  H03B3/04

    CPC classification number: H04L7/0337 ,  H04L7/0029

    Abstract: A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si), wherein the phasing is carried out in reference to the sampling instants. The phasing includes determining phasing test instants (Pi) which refer to the sampling instants (Si) to verify whether transitions of the digital signal are leading or lagging in phase relative to the phasing test instants. The determination of the phasing test instants is achieved by adding to each sampling instant (Si) a delay Y=kR/2, in which k is a positive whole odd number other than zero and R designates a pulse repetition period of the bits of the digital signal (D). The invention has particular utility in data processing and remote data processing systems, and to telecommunication systems.

    Abstract translation: 一种用于对串行数字信号（D）进行采样的处理和装置，其包括用时钟信号（C）对数字信号进行定相并在延迟时刻（Si）对数字信号进行采样，其中定相参照 抽样时刻。 定相包括确定参考采样时刻（Si）的相位测试时刻（Pi），以验证数字信号的转换是相对于定相测试时刻是在前进还是相位滞后。 定相测试时刻的确定是通过将​​延迟Y = kR / 2加到每个采样时刻（Si）来实现的，其中k是除零之外的正整数奇数，R表示 数字信号（D）。 本发明在数据处理和远程数据处理系统以及电信系统中具有特别的用途。

    Device for testing dynamic characteristics of components using serial transmissions
    2.
    发明授权
    Device for testing dynamic characteristics of components using serial transmissions 有权
    使用串行传输测试组件的动态特性的设备

    公开(公告)号：US06476615B1

    公开(公告)日：2002-11-05

    申请号：US09258476

    申请日：1999-02-26

    Applicant: Roland Marbot ,  Pascal Couteaux ,  Reza Nezamzadeh

    Inventor： Roland Marbot ,  Pascal Couteaux ,  Reza Nezamzadeh

    IPC: G01R2302

    CPC classification number: G01R31/30

    Abstract: A testing device for testing dynamic characteristics of an electronic circuit using serial transmissions. The circuit includes a multiplexing device and a demultiplexing device for implementing a serial link in the component or circuit. The testing device includes a transmitter for transmitting binary signals to the multiplexing device, a receiver for receiving binary signals from the demultiplexing device, and a link for selectively providing a coupling between the transmitter and the receiver. Additionally, a clock generator delivers a first clock signal to the transmitter and a second clock signal, which has a different frequency than the first clock signal, to the receiver. In one preferred embodiment, the clock generator includes a single programmable-frequency oscillator and a variable delay circuit. The programmable-frequency oscillator delivers the first clock signal and the variable delay circuit delays the first clock signal to deliver the second clock signal. The testing device can be used with circuits operating at frequencies in the range of 100 MHz. A method of testing dynamic characteristics of an electronic circuit using a testing device is also provided.

    Abstract translation: 一种用于测试使用串行传输的电子电路的动态特性的测试装置。 该电路包括多路复用装置和用于在组件或电路中实现串行链路的解复用装置。 测试装置包括用于将二进制信号发送到多路复用装置的发射机，用于从解复用装置接收二进制信号的接收机以及用于选择性地提供发射机和接收机之间的耦合的链路。 此外，时钟发生器向发射机提供第一时钟信号，并向接收机提供具有与第一时钟信号不同的频率的第二时钟信号。 在一个优选实施例中，时钟发生器包括单个可编程频率振荡器和可变延迟电路。 可编程频率振荡器提供第一时钟信号，并且可变延迟电路延迟第一时钟信号以递送第二时钟信号。 测试装置可以与在100 MHz范围内工作的电路一起使用。 还提供了使用测试装置测试电子电路的动态特性的方法。

    Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate
    4.
    发明授权
    Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate 有权
    具有四个二乘互补输入和两个互补输出的独占逻辑门，以及并入所述门的倍频器

    公开(公告)号：US6137309A

    公开(公告)日：2000-10-24

    申请号：US159316

    申请日：1998-09-23

    Applicant: Pascal Couteaux ,  Roland Marbot

    Inventor： Pascal Couteaux ,  Roland Marbot

    IPC: H03K5/00 ,  H03K19/21

    CPC classification number: H03K19/215 ,  H03K5/00006

    Abstract: An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

    Abstract translation: 具有四个二乘互补输入和两个互补输出的异或逻辑门。 据说这种异或门的结构是对称的，因为门的传播时间是相同的，两对互补输入中的任何一个都被切换，无论输出的转换的性质如何， 该对输入不切换。 所公开的装置能够通过消除某些节点的浮动特性来进一步减少通过门传播信号边缘所花费的时间差异。 它还涉及包括诸如此类的异或门树的倍频器。

    Device for receiving series data
    6.
    发明授权
    Device for receiving series data 有权
    用于接收系列数据的设备

    公开(公告)号：US07580496B2

    公开(公告)日：2009-08-25

    申请号：US10832803

    申请日：2004-04-26

    Applicant: Roland Marbot ,  Franck Hellard

    Inventor： Roland Marbot ,  Franck Hellard

    IPC: H03D3/24

    CPC classification number: H04L7/0337 ,  H03K5/133 ,  H03L7/091 ,  H04L7/0037

    Abstract: A circuit for receiving digital data arriving in series comprising a circuit for generating a reference dock and a circuit for oversampling the received data memorizing the samples sampled at the rate of several clocks phase-shifted with respect to the reference clock, the oversampling circuit comprising means for selecting and providing as output data samples representative of the received data and, further, a detection circuit identifying the variations of the phase shift between the reference clock edges and the transitions of the received data by analyzing the memorized samples, the detection circuit controlling a frequency variation of the reference dock when the phase shift variations repeat over several sampling cycles.

    Abstract translation: 一种用于接收数字数据串行电路的电路，包括用于产生参考基准的电路和用于对存储相对于参考时钟相移的几个时钟采样的采样采样的接收数据进行过采样的电路，该过采样电路包括： 用于选择和提供表示所接收数据的输出数据样本，以及另外，检测电路通过分析存储的样本来识别参考时钟边沿与接收数据的转变之间的相移的变化，检测电路控制 当相移变化在几个采样周期内重复时，参考基准的频率变化。

    Method and system for digital transmission of serial data
    8.
    发明授权
    Method and system for digital transmission of serial data 失效
    串行数据传输的方法和系统

    公开(公告)号：US5268937A

    公开(公告)日：1993-12-07

    申请号：US727430

    申请日：1991-07-09

    Applicant: Roland Marbot

    Inventor： Roland Marbot

    IPC: H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L25/40 ,  H04L23/00

    CPC classification number: H04L7/0337 ,  H04L7/048

    Abstract: The digital data transmission is of the type including the addition of clock and synchronizing information to the data to constitute the transmission signal, and the determination of the transmission speed from this received information. According to the invention, this information, in the transmission signal, comprises a synchronizing edge (SYNC) added to each group of N data bits (D0-D7, OP), and the determination of the transmission speed comprises producing N clock signals (CL0-CL9) from identical successive delays (480-489) of a synchronizing edge detected.

    Abstract translation: 数字数据传输是包括添加时钟和同步信息到数据以构成发送信号的类型，以及从该接收到的信息确定传输速度。 根据本发明，在发送信号中，该信息包括添加到每组N个数据比特（D0-D7，OP）的同步边缘（SYNC），并且传输速度的确定包括产生N个时钟信号（CL0 -CL9）从检测到的同步边缘的相同连续延迟（480-489）。

    High speed analog digital converter of the dichotomizing type
    9.
    发明授权
    High speed analog digital converter of the dichotomizing type 失效
    二分类型的高速模拟数字转换器

    公开(公告)号：US4675651A

    公开(公告)日：1987-06-23

    申请号：US724879

    申请日：1985-04-19

    Applicant: Roland Marbot ,  Jean-Pierre Polonovski

    Inventor： Roland Marbot ,  Jean-Pierre Polonovski

    IPC: H03M1/44 ,  H03M1/00

    CPC classification number: H03M1/366

    Abstract: A dichotomizing, high speed analog - digital comprises an input stage for the voltage - current conversion of the analog signal, a reference current source, a sequence of N-1 identical cells in series, each comprising a comparator and current dividers, a terminal cell incorporating a comparator, a digital coder receiving a digital signal from each cell and, optionally, a link positioned between the consecutive cells. The analog signal is processed in the cells entirely in current form, the link means making it possible to isolate the potentials between successive cells.

    Abstract translation: 二分法，高速模拟数字包​​括用于模拟信号的电压 - 电流转换的输入级，参考电流源，串联的N-1个相同单元的序列，每个包括比较器和电流分配器，终端单元 结合了比较器，数字编码器从每个单元接收数字信号，以及可选地，位于连续小区之间的链路。 模拟信号在电池中完全以当前形式进行处理，该连接装置使得可以隔离连续电池之间的电位。

    Monitoring of a program execution by the processor of an electronic circuit
    10.
    发明授权
    Monitoring of a program execution by the processor of an electronic circuit 有权
    监视由电子电路的处理器执行的程序

    公开(公告)号：US07607044B2

    公开(公告)日：2009-10-20

    申请号：US11509304

    申请日：2006-08-23

    Applicant: Gerard Humeau ,  Roland Marbot

    Inventor： Gerard Humeau ,  Roland Marbot

    IPC: G06F11/00

    CPC classification number: G06F11/3636

    Abstract: A method for monitoring the execution of a program by a processor of an electronic circuit comprises operations of collecting monitoring data within the circuit and of transmitting the monitoring data to a device for debugging the program. The monitoring data are transmitted via a connection external to the circuit, comprising at least one serial connection. The monitoring data are serialized within the circuit before being transmitted, then restored within the device for tuning the program.

    Abstract translation: 一种用于监视由电子电路的处理器执行程序的方法包括收集电路内的监视数据并将监视数据发送到用于调试程序的设备的操作。 监视数据经由电路外部的连接发送，包括至少一个串行连接。 监控数据在发送之前在电路内串行化，然后在设备内恢复以调谐程序。

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