公开(公告)号：US08227264B2

公开(公告)日：2012-07-24

申请号：US13071894

申请日：2011-03-25

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L21/30

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US07936060B2

公开(公告)日：2011-05-03

申请号：US12431827

申请日：2009-04-29

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L23/52

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US08592932B2

公开(公告)日：2013-11-26

申请号：US13430195

申请日：2012-03-26

申请人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

IPC分类号： H01L31/0203

CPC分类号： H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

公开(公告)号：US08080876B2

公开(公告)日：2011-12-20

申请号：US12147466

申请日：2008-06-26

申请人： Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

IPC分类号： H01L23/538

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

摘要翻译： 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

公开(公告)号：US20090039472A1

公开(公告)日：2009-02-12

申请号：US12147466

申请日：2008-06-26

申请人： Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John U. Knickerbocker ,  Michelle L. Steen ,  Cornelia K. Tsang

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

摘要翻译： 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

公开(公告)号：US20080284037A1

公开(公告)日：2008-11-20

申请号：US11748818

申请日：2007-05-15

申请人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。

公开(公告)号：US08012796B2

公开(公告)日：2011-09-06

申请号：US12538223

申请日：2009-08-10

申请人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。

公开(公告)号：US20100013073A1

公开(公告)日：2010-01-21

申请号：US12543827

申请日：2009-08-19

申请人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

IPC分类号： H01L23/52

CPC分类号： H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。

公开(公告)号：US20090311828A1

公开(公告)日：2009-12-17

申请号：US12538223

申请日：2009-08-10

申请人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

IPC分类号： H01L21/768 ,  H01L21/50

CPC分类号： H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。

公开(公告)号：US09159602B2

公开(公告)日：2015-10-13

申请号：US12543827

申请日：2009-08-19

申请人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  John U. Knickerbocker ,  Cornelia K. Tsang

IPC分类号： H01L23/02 ,  H01L21/683 ,  H01L23/14 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

摘要翻译： 提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。