公开(公告)号：US11640838B2

公开(公告)日：2023-05-02

申请号：US17448846

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Changho Jung ,  Chulmin Jung

IPC: G11C11/418 ,  G11C7/22 ,  G11C7/10 ,  H03K19/21 ,  G11C7/06 ,  G11C5/14

Abstract: A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.

公开(公告)号：US11250895B1

公开(公告)日：2022-02-15

申请号：US17089534

申请日：2020-11-04

Applicant: QUALCOMM Incorporated

Inventor： Dhvani Sheth ,  Anil Chowdary Kota ,  Hochul Lee ,  Chulmin Jung ,  Bin Liang

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/30 ,  G11C7/10

Abstract: A memory device including: a first core of memory bitcells; a second core of memory bitcells; pre-decoding circuitry shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder including a first set-reset (SR) latch coupled to a first wordline of the first core and a second SR latch coupled to a second wordline of the second core.

公开(公告)号：US20180046209A1

公开(公告)日：2018-02-15

申请号：US15791226

申请日：2017-10-23

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

公开(公告)号：US09536578B2

公开(公告)日：2017-01-03

申请号：US13863989

申请日：2013-04-16

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

IPC: G11C7/12 ,  G11C7/10 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。

公开(公告)号：US09484110B2

公开(公告)日：2016-11-01

申请号：US13953511

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Chulmin Jung ,  Esin Terzioglu ,  Steven Mark Millendorf

IPC: G11C17/12 ,  G11C7/24

CPC classification number: G11C17/12 ,  G11C7/24

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word lines. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract translation: 掩模编程的只读存储器（MROM）具有多个列线对，每一列具有位线和补码位线。 MROM包括与列线对和多个字线之间的多个交点相对应的多个存储单元。 每个存储单元包括高Vt晶体管和低Vt晶体管。

公开(公告)号：US20150269978A1

公开(公告)日：2015-09-24

申请号：US14218691

申请日：2014-03-18

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Rui Li ,  Sei Seung Yoon ,  Gregory Ameriada Uvieghara

IPC: G11C7/06 ,  G11C17/16

CPC classification number: G11C7/062 ,  G11C17/16 ,  G11C17/18 ,  H03F3/45183 ,  H03F3/45497 ,  H03F2203/45402 ,  H03F2203/45604 ,  H03F2203/45641 ,  H03F2203/45652

Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.

Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。

公开(公告)号：US08860493B2

公开(公告)日：2014-10-14

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

公开(公告)号：US12125526B2

公开(公告)日：2024-10-22

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Xiao Chen ,  Chi-Jui Chen ,  Anil Chowdary Kota ,  Dhvani Sheth

IPC: G11C5/14 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

公开(公告)号：US12047073B2

公开(公告)日：2024-07-23

申请号：US17922176

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K5/00

CPC classification number: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K2005/00078

Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

公开(公告)号：US12014771B2

公开(公告)日：2024-06-18

申请号：US18175023

申请日：2023-02-27

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Arun Babu Pallerla ,  Chulmin Jung

IPC: G11C11/419 ,  G11C11/413 ,  H03K19/20

CPC classification number: G11C11/419 ,  G11C11/413 ,  H03K19/20

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.