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    Protected data streaming between memories
    1.
    发明授权
    Protected data streaming between memories 有权

    公开(公告)号：US11630723B2

    公开(公告)日：2023-04-18

    申请号：US17147110

    申请日：2021-01-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： Yanru Li ,  Dexter Tamio Chun

    IPC: H04L9/08 ,  G06F11/10 ,  G06F16/907

    Abstract: Transferring data between memories may include reading data associated with a memory transfer transaction from a first memory, determining whether a bypass indication associated with the memory transfer transaction is asserted, and transferring the data from the first memory to a second memory. The transferring may include bypassing the first-processing if the bypass indication is asserted. The transferring may further include bypassing second-processing the data if the bypass indication is asserted. Following bypassing the second-processing, the data may be stored in the second memory.

    Enhanced data clock operations in memory
    2.
    发明授权
    Enhanced data clock operations in memory 有权

    公开(公告)号：US11175836B2

    公开(公告)日：2021-11-16

    申请号：US16803977

    申请日：2020-02-27

    Applicant: Qualcomm Incorporated

    Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

    IPC: G06F3/06 ,  G06F12/0875

    Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

    Partial refresh technique to save memory refresh power
    4.
    发明授权
    Partial refresh technique to save memory refresh power 有权

    公开(公告)号：US10726904B2

    公开(公告)日：2020-07-28

    申请号：US16362427

    申请日：2019-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

    IPC: G11C13/06 ,  G11C11/406 ,  G11C7/10 ,  G11C8/12

    Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

    Systems and methods for optimizing memory power consumption in a heterogeneous system memory
    6.
    发明授权
    Systems and methods for optimizing memory power consumption in a heterogeneous system memory 有权

    公开(公告)号：US10157008B2

    公开(公告)日：2018-12-18

    申请号：US14699431

    申请日：2015-04-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： Dexter Tamio Chun ,  Yanru Li

    IPC: G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F12/06 ,  G06F9/4401

    Abstract: Systems, methods, and computer programs are disclosed for providing a heterogeneous system memory in a portable communication device. One system comprises a system on chip (SoC) coupled to a nonvolatile random access memory (NVRAM) and a volatile random access memory (VRAM). The SoC comprises an operating system for mapping a heterogeneous system memory comprising the NVRAM and the VRAM. The operating system comprises a memory manager configured to allocate a first portion of the NVRAM as a block device for a swap operation, a second portion of the NVRAM for program code and read-only data, and a third portion of the NVRAM for operating system page tables. The VRAM is allocated for a program heap and a program stack.

    Systems and methods for providing improved latency in a non-uniform memory architecture
    10.
    发明授权
    Systems and methods for providing improved latency in a non-uniform memory architecture 有权
    用于在非均匀存储器架构中提供改进的延迟的系统和方法

    公开(公告)号：US09575881B2

    公开(公告)日：2017-02-21

    申请号：US14560290

    申请日：2014-12-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： Stephen Arthur Molloy ,  Dexter Tamio Chun

    IPC: G06F12/02 ,  G11C7/10 ,  G06F12/10

    CPC classification number: G06F12/023 ,  G06F12/0223 ,  G06F12/1072 ,  G06F15/163 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/2542 ,  G11C7/1072 ,  G11C7/1075

    Abstract: Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining a free physical page pair comprising a same physical address available on the first and second local volatile memory devices; and mapping the free physical page pair to a single virtual page address.

    Abstract translation: 公开了用于在具有非均匀存储器架构的便携式计算设备中分配存储器的系统，方法和计算机程序。 一种方法的一个实施例包括：从在第一片上系统（SoC）上执行对虚拟存储器页的请求的处理，所述第一SoC经由芯片间接口电耦合到第二SoC，所述第一SoC电耦合到 第一本地易失性存储器设备经由第一高性能总线，并且所述第二SoC经由第二高性能总线电耦合到第二本地易失性存储器设备; 确定包括在所述第一和第二本地易失性存储器设备上可用的相同物理地址的空闲物理页对; 并将自由物理页对映射到单个虚拟页地址。

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