公开(公告)号：US20240264950A1

公开(公告)日：2024-08-08

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

CPC classification number: G06F12/126 ,  G06F12/0888 ,  G06F2212/502

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US12235699B2

公开(公告)日：2025-02-25

申请号：US18166381

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Vijayakumar Ashok Dibbad ,  Nikhil Ashok Bhelave ,  Jeffrey Gemar ,  Matthew Severson

IPC: G06F1/30

Abstract: Various embodiments include methods performed by a processor for managing voltage droop margins of a power distribution network (PDN). Various embodiments may include receiving, by a processor from a first client powered by a shared power rail within the PDN, a first requested performance corner, receiving, by the processor from a second client powered by the shared power rail, a second requested performance corner, determining by the processor a first peak current value based on the first requested performance corner, determining by the processor a second peak current value based on the second requested performance corner, determining by the processor a system voltage droop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN, and adjusting a voltage of the shared power rail based on the system voltage droop margin.

公开(公告)号：US12182036B2

公开(公告)日：2024-12-31

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US09965220B2

公开(公告)日：2018-05-08

申请号：US15016806

申请日：2016-02-05

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Haw-Jing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US11636057B2

公开(公告)日：2023-04-25

申请号：US17390215

申请日：2021-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： Engin Ipek ,  Bohuslav Rychlik ,  George Patsilaras ,  Prajakt Kulkarni ,  Can Hankendi ,  Fahad Ali ,  Jeffrey Gemar ,  Matthew Severson

IPC: G06F13/16 ,  H03M5/14

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

公开(公告)号：US10761774B2

公开(公告)日：2020-09-01

申请号：US15944041

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Michael Hawjing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F1/32 ,  G06F12/08 ,  G06F3/06 ,  G06F1/3234

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US09612636B2

公开(公告)日：2017-04-04

申请号：US14497258

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Matthew Levi Severson ,  Shih-Hsin Jason Hu ,  Dipti Ranjan Pal ,  Madan Krishnappa ,  Jeffrey Gemar ,  Noman Ahmed ,  Mohammad Tamjidi ,  Mark Kempfert

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/44

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.

公开(公告)号：US11029745B2

公开(公告)日：2021-06-08

申请号：US16184934

申请日：2018-11-08

Applicant: QUALCOMM INCORPORATED

Inventor： Kyle Ernewein ,  Jason Edward Podaima ,  Francisco Perez ,  John Daniels ,  Alex Miler ,  Jeffrey Gemar ,  Rexford Alan Hill ,  Haoping Xu

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3228

Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.

公开(公告)号：US10915157B2

公开(公告)日：2021-02-09

申请号：US16276532

申请日：2019-02-14

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Jeffrey Gemar ,  Abinash Roy

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/3203

Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.

公开(公告)号：US20180225066A1

公开(公告)日：2018-08-09

申请号：US15944041

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Michael Hawjing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F3/06 ,  G06F1/32 ,  G06F12/08

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.