公开(公告)号：US11984900B2

公开(公告)日：2024-05-14

申请号：US17934654

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jianjun Yu ,  Yue Chao ,  Tomas O'Sullivan ,  Lai Kan Leung

IPC: H03L7/099 ,  H03B5/12 ,  H03K3/0231 ,  H03M1/46

CPC classification number: H03L7/099 ,  H03B5/1293 ,  H03K3/0231 ,  H03M1/46

Abstract: Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

公开(公告)号：US10990117B2

公开(公告)日：2021-04-27

申请号：US16561839

申请日：2019-09-05

Applicant: QUALCOMM Incorporated

Inventor： Yue Chao ,  Marco Zanuso ,  Rajagopalan Rangarajan ,  Yiwu Tang

IPC: G05F1/575 ,  G05F1/595

Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

公开(公告)号：US11387833B1

公开(公告)日：2022-07-12

申请号：US17466901

申请日：2021-09-03

Applicant: QUALCOMM Incorporated

Inventor： Alvin Siu-Chi Li ,  Yue Chao ,  Dongmin Park ,  Heui In Yoon ,  Tomas O'Sullivan ,  Jianjun Yu ,  Yiwu Tang

IPC: H03L7/089 ,  G04F10/00 ,  H04L7/033

Abstract: A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.

公开(公告)号：US11342927B1

公开(公告)日：2022-05-24

申请号：US17361217

申请日：2021-06-28

Applicant: QUALCOMM Incorporated

Inventor： Younghyun Lim ,  Yiwu Tang ,  Dongmin Park ,  Yunliang Zhu ,  Mustafa Keskin ,  Yue Chao

IPC: H03L7/099 ,  H03K21/08 ,  H03K23/66 ,  H03L7/191

Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

公开(公告)号：US11290058B2

公开(公告)日：2022-03-29

申请号：US17076998

申请日：2020-10-22

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Chao ,  Yinghan Wang ,  Marco Zanuso ,  Rajagopalan Rangarajan

IPC: H03B5/12 ,  H03L7/093 ,  H03L7/08

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

公开(公告)号：US11264995B1

公开(公告)日：2022-03-01

申请号：US17079795

申请日：2020-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Chao ,  Yiwu Tang ,  Yunliang Zhu ,  Dongmin Park ,  Jingcheng Zhuang

IPC: H03B19/00 ,  H03L7/197 ,  H03L7/099 ,  H03K5/00

Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.

公开(公告)号：US11025260B1

公开(公告)日：2021-06-01

申请号：US17003923

申请日：2020-08-26

Applicant: Qualcomm Incorporated

Inventor： Yue Chao ,  Marco Zanuso ,  Rajagopalan Rangarajan ,  Yiwu Tang

IPC: H03L7/099 ,  H03L7/197 ,  H03L7/089 ,  H03L7/093

Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.