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    STARTUP CIRCUIT AND METHODS OF USE FOR AUDIO ACCESSORIES
    4.
    发明申请
    STARTUP CIRCUIT AND METHODS OF USE FOR AUDIO ACCESSORIES 审中-公开

    公开(公告)号：US20180146276A1

    公开(公告)日：2018-05-24

    申请号：US15472017

    申请日：2017-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Meysam Azin ,  Hui-ya Liao Nelson ,  Mark Cherry ,  Jingxue Lu

    IPC: H04R1/10 ,  G06F3/16 ,  H03H7/32

    CPC classification number: H04R1/1041 ,  G06F3/165 ,  H03H7/32 ,  H04R2420/09

    Abstract: An accessory device, configured to be interfaced with a master device, and configured to operate in an analog mode and in a digital mode, the accessory device including: a startup circuit including: a first transistor that interfaces the accessory device to the master device, wherein the first transistor is configured with a first resistive capacitive (RC) circuit to turn on the first transistor according to a time constant of the first RC circuit; a second transistor coupled between ground and the first RC circuit, wherein the second transistor is configured to control a gate of the first transistor in response to a control signal; and a diode having an anode coupled to the first node and a cathode coupled to a body terminal of the first transistor.

    Differentiating-integrating sampling data receiver
    5.
    发明授权
    Differentiating-integrating sampling data receiver 有权

    公开(公告)号：US09979533B2

    公开(公告)日：2018-05-22

    申请号：US15255562

    申请日：2016-09-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： Matthew David Sienko ,  Meysam Azin ,  Weibo Hu

    IPC: H04L7/02 ,  H04L7/00 ,  H04L25/06

    CPC classification number: H04L7/0087 ,  H04L25/069 ,  H04L25/08

    Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

    Input/output (I/O) driver
    6.
    发明授权
    Input/output (I/O) driver 有权
    输入/输出（I / O）驱动

    公开(公告)号：US09473127B1

    公开(公告)日：2016-10-18

    申请号：US14792361

    申请日：2015-07-06

    Applicant: QUALCOMM Incorporated

    Inventor： Meysam Azin

    IPC: H03K3/00 ,  H03K5/04 ,  H03K19/0185 ,  H03K19/00

    CPC classification number: H03K5/04 ,  H03K19/0016 ,  H03K19/00361 ,  H03K19/018507

    Abstract: An I/O driver and related method are provided herein. The I/O driver includes circuitry for expediting the configuring of the corresponding output FET to operate in the linear region to reduce delay between the transition of the input signal and the corresponding transition of the output signal. Additionally, the I/O driver includes circuitry for controlling the slew rate at which the output signal transitions from a low logic state to a high logic state, or vice-versa. Further, the I.O driver includes circuitry for turning off the turned-on output FET before turning on the other output FET. This prevents “shoot-thru” current from flowing through the output FETs to reduce power consumption associated with the I/O driver.

    Abstract translation: 本文提供了I / O驱动程序及相关方法。 I / O驱动器包括用于加速配置相应的输出FET以在线性区域中操作以减少输入信号的转变与输出信号的相应转变之间的延迟的电路。 此外，I / O驱动器包括用于控制输出信号从低逻辑状态转换到高逻辑状态的转换速率的电路，反之亦然。 此外，I.O驱动器包括在接通另一输出FET之前关断导通输出FET的电路。 这样可以防止“直通”电流流过输出FET，从而降低与I / O驱动器相关的功耗。

    Transmitter output signal power measurement apparatus
    7.
    发明授权
    Transmitter output signal power measurement apparatus 有权

    公开(公告)号：US11546004B2

    公开(公告)日：2023-01-03

    申请号：US17211769

    申请日：2021-03-24

    Applicant: QUALCOMM Incorporated

    Inventor： Meysam Azin ,  Li Lu ,  Anees Habib ,  Chinmaya Mishra ,  Damin Cao ,  Arul Balasubramaniyan ,  David Ta-hsiang Lin ,  Shuang Zhu ,  Dinesh Jagannath Alladi

    IPC: H04B1/04 ,  H03M3/00 ,  H03M1/46

    Abstract: Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

    CONTROL CIRCUITS FOR GENERATING OUTPUT ENABLE SIGNALS, AND RELATED SYSTEMS AND METHODS
    9.
    发明申请
    CONTROL CIRCUITS FOR GENERATING OUTPUT ENABLE SIGNALS, AND RELATED SYSTEMS AND METHODS 有权
    用于产生输出使能信号的控制电路及相关系统和方法

    公开(公告)号：US20160306382A1

    公开(公告)日：2016-10-20

    申请号：US14713058

    申请日：2015-05-15

    Applicant: QUALCOMM Incorporated

    Inventor： Lior Amarilio ,  Meysam Azin ,  Alexander Khazin ,  Le Wang

    IPC: G06F1/10 ,  G06F1/06

    CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F13/4291

    Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

    Abstract translation: 公开了用于产生输出使能信号的控制电路。 在一个方面，提供了一种控制电路，其采用组合逻辑来产生使用标准时钟信号满足定时约束的输出使能信号，基于标准时钟信号的反馈时钟信号和单个数据速率（SDR）数据输出 流。 控制电路包括双数据速率（DDR）转换电路，配置为基于接收到的SDR输出流生成DDR输出流。 控制电路包括输出使能电路，其被配置为接收标准时钟信号，反馈时钟信号和DDR输出流，并且根据定义的时序约束生成被断言和解除断言的输出使能信号。 控制电路被配置为产生精确定时的输出使能信号，而不需要除了标准时钟信号之外的快速时钟信号。

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