公开(公告)号：US20250096737A1

公开(公告)日：2025-03-20

申请号：US18470310

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xingyi HUA ,  Hsiao-Tsung YEN ,  David Zixiang YANG ,  Mehmet UZUNKOL

IPC: H03F1/26 ,  H03H7/01 ,  H03H7/06 ,  H03H7/09 ,  H04B1/40

Abstract: A low-noise amplifier (LNA) includes a first transistor, a first source inductor coupled to a source of the first transistor, and a second transistor, wherein a source of the second transistor is coupled to a drain of the first transistor, a gate of the second transistor is coupled to a bias circuit, and a drain of the second transistor is coupled to an output of the LNA. The LNA also includes an output inductor coupled between a supply rail and the output of the LNA, wherein the output inductor is magnetically coupled with the first source inductor.

公开(公告)号：US20240321936A1

公开(公告)日：2024-09-26

申请号：US18189110

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Hsiao-Tsung YEN ,  Xingyi HUA ,  Jeongil Jay KIM

IPC: H01L23/552 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/552

Abstract: An integrated device comprising a die substrate, a die interconnection portion coupled to the die substrate, an inductor, and a shield structure. The shield structure comprises a shield frame and a plurality of shield branches coupled to the shield frame, wherein at least one shield branch from the plurality of shield branches comprises a repeating wave shape.

公开(公告)号：US20240321497A1

公开(公告)日：2024-09-26

申请号：US18189910

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Hsiao-Tsung YEN ,  Xingyi HUA ,  Jeongil Jay KIM

IPC: H01F17/00 ,  H01L23/498

CPC classification number: H01F17/0013 ,  H01L23/49822 ,  H01L28/10 ,  H01F2017/002 ,  H01F2017/0086 ,  H01L24/16 ,  H01L2224/16227

Abstract: An integrated device comprising a die substrate; and a die interconnection portion coupled to the die substrate. The die interconnection comprises a first inductor and a second inductor. The first inductor comprises a first spiral comprising a first origin and a first tail and a second spiral comprising a second origin and a second tail.

公开(公告)号：US20230231586A1

公开(公告)日：2023-07-20

申请号：US17580320

申请日：2022-01-20

Applicant: QUALCOMM Incorporated

Inventor： Xingyi HUA ,  Bassel HANAFI ,  Karthik TRIPURARI JAYARAMAN ,  Francesco GATTA

IPC: H04B1/04 ,  H03F1/56

CPC classification number: H04B1/0483 ,  H03F1/565 ,  H04B2001/0416 ,  H03F2200/451

Abstract: Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry implementing a low noise amplifier (LNA) with phase-shifting circuitry to achieve a continuous phase at the output of the LNA. One aspect is an amplifier including a high gain active path comprising active circuitry, and a low gain path comprising passive circuitry and phase-shifting circuitry. In one or more aspects, the phase-shifting circuitry is configured to shift a phase of an input signal within the low gain path such that the phase of an output signal outputted from the low gain path approximately matches a phase of an output signal outputted from the high gain active path. In at least one aspect, a gain of the high gain active path is higher than a gain of the low gain passive path.

公开(公告)号：US20230179181A1

公开(公告)日：2023-06-08

申请号：US17457840

申请日：2021-12-06

Applicant: QUALCOMM Incorporated

Inventor： Xingyi HUA

IPC: H03H19/00 ,  H02M1/14

CPC classification number: H03H19/004 ,  H02M1/14

Abstract: In certain aspects, a system includes a voltage line, a switched-capacitor circuit coupled to the voltage line, and a ripple-cancellation circuit. The ripple-cancellation circuit includes a current mirror having a first branch and a second branch, wherein the second branch of the current mirror is coupled to the voltage line, a switching circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the switching circuit is coupled to the first branch of the current mirror, and the third terminal is coupled to a ground or a reference voltage, and a first capacitor coupled to the second terminal of the switching circuit.

公开(公告)号：US20250141406A1

公开(公告)日：2025-05-01

申请号：US18499682

申请日：2023-11-01

Applicant: QUALCOMM Incorporated

Inventor： Xingyi HUA ,  Hsiao-Tsung YEN ,  Mehmet UZUNKOL

IPC: H03F1/22 ,  H03F1/56 ,  H03F3/72

Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes: an active path coupled between an input node of the amplifier and an output node of the amplifier, wherein the active path comprises a first transistor coupled to the input node of the amplifier and a first inductive element coupled between the first transistor and the output node; and a bypass path coupled between the input node of the amplifier and the output node of the amplifier, the bypass path also comprising the first inductive element.

公开(公告)号：US20240310887A1

公开(公告)日：2024-09-19

申请号：US18121508

申请日：2023-03-14

Applicant: QUALCOMM Incorporated

Inventor： Xingyi HUA ,  David Zixiang YANG ,  Francesco GATTA

IPC: G06F1/26 ,  H04M1/725

CPC classification number: G06F1/26 ,  H04M1/725 ,  H04M2201/02 ,  H04M2201/04 ,  H04M2201/06 ,  H04M2201/14

Abstract: A dual-VIO integrated circuit is configurable into either a first configuration in which a VIO power supply voltage has a first value or into a second configuration in which the VIO power supply voltage has a second value. The dual-VIO integrated circuit includes a smart start-up detection circuit that detects whether the integrated circuit is in the first configuration or the second configuration.

公开(公告)号：US20230327693A1

公开(公告)日：2023-10-12

申请号：US17658379

申请日：2022-04-07

Applicant: QUALCOMM Incorporated

Inventor： Karthik TRIPURARI JAYARAMAN ,  Bao Huu LAM ,  Xingyi HUA

IPC: H04B1/10 ,  H04K3/00 ,  H03F1/26 ,  H04B1/04 ,  H03H7/01

CPC classification number: H04B1/1036 ,  H04K3/20 ,  H03F1/26 ,  H04B1/0475 ,  H03H7/01 ,  H04B1/0458 ,  H03H2007/013

Abstract: Techniques for providing low-cost and effective jammer rejection for an amplifier is disclosed. The amplifier includes an input node and an output node, a first transistor and a second transistor, a load circuitry, an inductor, and a capacitor. A first terminal of the first transistor is coupled to a ground. A second terminal of the first transistor is coupled to a first terminal of the second transistor. A second terminal of the second transistor is coupled to the output node. The load circuitry is coupled between a power supply and the second terminal of the second transistor. A first terminal of the inductor is coupled to the ground through a first switch. A first terminal of the capacitor is coupled to the first terminal of the second transistor and a second terminal of the capacitor is coupled to a second terminal of the inductor.

公开(公告)号：US20250132736A1

公开(公告)日：2025-04-24

申请号：US18829889

申请日：2024-09-10

Applicant: QUALCOMM Incorporated

Inventor： Alaaeldien Mohamed Abdelrazek MEDRA ,  Xingyi HUA ,  Naushad DHAMANI ,  Francesco GATTA

IPC: H03F3/19 ,  H04B1/16

Abstract: Aspects of the present disclosure relate to a receiver including an amplifier circuit. The amplifier circuit includes a common-source amplifier having an input and an output, and a common-gate amplifier having an input and an output, wherein the input of the common-gate amplifier is coupled to the output of the common-source amplifier. The receiver also includes a first receive chain coupled to the output of the common-gate amplifier, and a second receive chain coupled to the output of the common-source amplifier.

公开(公告)号：US20240321730A1

公开(公告)日：2024-09-26

申请号：US18189673

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Hsiao-Tsung YEN ,  Xingyi HUA ,  Jeongil Jay KIM

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0231 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2105

Abstract: An integrated device comprising a die substrate, a die interconnection portion coupled to the die substrate, and a stacked inductor that includes a first figure 8-shaped inductor and a second figure 8-shaped inductor. The stacked inductor may include a first spiral comprising a first origin and a first tail, a second spiral comprising a second origin and a second tail, a third spiral comprising a third origin and a third tail and a fourth spiral comprising a fourth origin and a fourth tail. The first spiral, the second spiral, the third spiral and the fourth spiral may form the first figure 8-shaped inductor and the second figure 8-shaped inductor. The stacked inductor may be located in the die interconnection.