公开(公告)号：US11024361B2

公开(公告)日：2021-06-01

申请号：US15400507

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Jungwon Suh

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4091 ,  G11C8/12

Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

公开(公告)号：US10338837B1

公开(公告)日：2019-07-02

申请号：US15946600

申请日：2018-04-05

Applicant: QUALCOMM Incorporated

Inventor： Subrato Kumar De ,  Dexter Tamio Chun ,  Yanru Li ,  Bohuslav Rychlik ,  Richard Alan Stewart

IPC: G06F3/06 ,  G06N20/00

Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.

公开(公告)号：US10180908B2

公开(公告)日：2019-01-15

申请号：US14710693

申请日：2015-05-13

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Azzedine Touzni

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0888 ,  G06F12/084 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/1045

Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

公开(公告)号：US10089238B2

公开(公告)日：2018-10-02

申请号：US14334010

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edmund Turner ,  Jeong-Ho Woo

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F9/50 ,  G06F12/0888 ,  G06F12/0864 ,  G06F1/32 ,  G06F17/30

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

公开(公告)号：US09785371B1

公开(公告)日：2017-10-10

申请号：US15081915

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Tamio Chun ,  Alain Artieri

IPC: G06F1/32 ,  G06F3/06 ,  G06F12/0862 ,  G11C11/406

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  Y02D10/13

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：US09778871B1

公开(公告)日：2017-10-03

申请号：US15081914

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Tamio Chun ,  Alain Artieri

IPC: G06F1/32 ,  G06F3/06 ,  G06F12/0862 ,  G11C11/406 ,  G11C7/10

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/0862 ,  G06F13/1689 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  G11C2211/4067 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：US09507675B2

公开(公告)日：2016-11-29

申请号：US14253770

申请日：2014-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Yanru Li ,  Jung Pill Kim ,  Deepti Vijayalakshmi Sriramagiri

IPC: G06F11/20 ,  G06F11/10 ,  G06F11/14 ,  G06F11/07 ,  G06F11/08 ,  G11C29/00 ,  G11C29/52 ,  G06F3/06 ,  G11C29/08

CPC classification number: G06F11/2017 ,  G06F3/0688 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1417 ,  G06F2201/85 ,  G06F2212/1032 ,  G06F2212/7201 ,  G11C29/00 ,  G11C29/08 ,  G11C29/52 ,  G11C29/70

Abstract: Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation.

Abstract translation: 公开了用于从动态随机存取存储器（DRAM）缺陷中恢复的系统，方法和计算机程序。 一种方法包括确定与耦合到片上系统（SoC）的动态随机存取存储器（DRAM）设备相关联的物理码字地址已经发生未校正的位错误。 与包括物理码字地址的DRAM页面相关联的内核页面被识别为坏页面。 通过重新启动包括SoC和DRAM设备的系统来提供从未校正的位错误的恢复。 响应于重新启动，识别的内核页面被排除在为DRAM操作分配之前。

公开(公告)号：US09495261B2

公开(公告)日：2016-11-15

申请号：US14458009

申请日：2014-08-12

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Dexter Tamio Chun ,  Deepti Vijayalakshmi Sriramagiri ,  Mosaddiq Saifuddin ,  Xiangyu Dong ,  Sungryul Kim ,  Yanru Li ,  Jungwon Suh

IPC: G06F11/00 ,  G06F11/20 ,  G11C29/52 ,  G06F11/08 ,  G06F11/30 ,  G11C29/44 ,  G11C29/04

CPC classification number: G06F11/2053 ,  G06F11/073 ,  G06F11/0775 ,  G06F11/0793 ,  G06F11/08 ,  G06F11/1048 ,  G06F11/3037 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0409

Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.

Abstract translation: 提供了修复或尝试修复存​​储器件中的随机位故障的系统内修复过程的方法和系统。 在一些示例中，系统内修复过程可以根据故障是可校正还是不可校正来选择替代步骤。 在这些示例中，该过程使用片上系统与存储器之间的通信来在正常操作期间修复故障。

公开(公告)号：US11630723B2

公开(公告)日：2023-04-18

申请号：US17147110

申请日：2021-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Tamio Chun

IPC: H04L9/08 ,  G06F11/10 ,  G06F16/907

Abstract: Transferring data between memories may include reading data associated with a memory transfer transaction from a first memory, determining whether a bypass indication associated with the memory transfer transaction is asserted, and transferring the data from the first memory to a second memory. The transferring may include bypassing the first-processing if the bypass indication is asserted. The transferring may further include bypassing second-processing the data if the bypass indication is asserted. Following bypassing the second-processing, the data may be stored in the second memory.

公开(公告)号：US10817224B2

公开(公告)日：2020-10-27

申请号：US15191400

申请日：2016-06-23

Applicant: QUALCOMM INCORPORATED

Inventor： Subrato Kumar De ,  Dexter Chun ,  Yanru Li

IPC: G06F3/06 ,  G06F9/445 ,  G06F12/02 ,  G06F8/61

Abstract: Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.