Abstract:
The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.
Abstract:
The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.
Abstract:
The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.
Abstract:
A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group.
Abstract:
A system and method for performing a low overhead refresh management of a memory device. The method includes receiving, by a controller from a dynamic random access memory (DRAM) device via a feedback interface, a signal indicative of an occurrence of a row hammer event. The method includes determining, by the controller based on the signal, whether to schedule a refresh event. The method includes sending, by the controller responsive to determining whether to schedule the refresh event, a first command to the DRAM device to execute a refresh operation.
Abstract:
The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.
Abstract:
Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.
Abstract:
A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group.
Abstract:
Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.
Abstract:
The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.