公开(公告)号：US20200035552A1

公开(公告)日：2020-01-30

申请号：US16592869

申请日：2019-10-04

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  C23C14/06 ,  C23C14/16 ,  C23C14/34 ,  H01L21/285

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20170040212A1

公开(公告)日：2017-02-09

申请号：US15298302

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/34 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract translation: 提高了半导体器件的性能。 在一个实施例中，例如，沉积时间从4.6秒增加到6.9秒。 换句话说，在一个实施例中，通过增加沉积时间来增加氮化钽膜的厚度。 具体地，在一个实施例中，沉积时间增加，使得设置在要连接到宽互连件的连接孔的底部上的氮化钽膜具有在5至10nm的范围内的厚度。

公开(公告)号：US20220384257A1

公开(公告)日：2022-12-01

申请号：US17887045

申请日：2022-08-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  C23C14/06 ,  C23C14/16 ,  C23C14/34 ,  H01L21/285

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20200043857A1

公开(公告)日：2020-02-06

申请号：US16521090

申请日：2019-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naohito SUZUMURA ,  Kazuyuki OMORI

IPC: H01L23/532 ,  H01L21/768

Abstract: In the semiconductor device, a first defect formation preventing film is formed on the first wiring side, and a second defect formation preventing film is formed on the second wiring side. when a ratio of an infrared absorption intensity corresponding to a bond between silicon and hydrogen to an infrared absorption intensity corresponding to a bond between silicon and oxygen is defined as an abundance ratio, the abundance ratio in the first defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film. The abundance ratio in the second defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film.

公开(公告)号：US20200251385A1

公开(公告)日：2020-08-06

申请号：US16854957

申请日：2020-04-22

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/285 ,  C23C14/34 ,  C23C14/16 ,  C23C14/06

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20160079188A1

公开(公告)日：2016-03-17

申请号：US14952618

申请日：2015-11-25

Applicant: Renesas Electronics Corporation

Inventor： Kazuhito ICHINOSE ,  Seiji MURANAKA ,  Kazuyuki OMORI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/564 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76835 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48844 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.

公开(公告)号：US20180240700A1

公开(公告)日：2018-08-23

申请号：US15953948

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  C23C14/06 ,  H01L21/285 ,  C23C14/16 ,  C23C14/34

CPC classification number: H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/34 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20160300804A1

公开(公告)日：2016-10-13

申请号：US15072148

申请日：2016-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki OMORI

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L21/48 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76855 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/564 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01029 ,  H01L2924/00014

Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent electric short-circuiting between redistribution lines. A barrier film is formed over each side surface of a copper redistribution line. The barrier film includes, for example, a manganese oxide film. The barrier film is also in contact with each end surface of a barrier metal film that is located in the position receding inward from the side surface of the copper redistribution line. A redistribution portion is formed by the copper redistribution line, the barrier film, and the barrier metal film.

Abstract translation: 提供了可以防止再分配线之间的电短路的半导体器件及其制造方法。 在铜再分配线的每个侧表面上形成阻挡膜。 阻挡膜包括例如氧化锰膜。 阻挡膜也与位于从铜再分布线的侧面向内侧退避的位置的阻挡金属膜的各端面接触。 再分配部分由铜再分配线，阻挡膜和阻挡金属膜形成。

公开(公告)号：US20230345734A1

公开(公告)日：2023-10-26

申请号：US18179720

申请日：2023-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki OMORI ,  Tadashi YAMAGUCHI

IPC: H10B51/30

CPC classification number: H10B51/30

Abstract: A ferroelectric memory cell includes a paraelectric film formed on a semiconductor substrate and a ferroelectric layer formed on the paraelectric film. The ferroelectric layer includes ferroelectric films and a plurality of grains. The ferroelectric films are made of a material containing a metal oxide and a first element. The plurality of grains are made of a material different from the material forming the ferroelectric films, and are made of a ferroelectric.

公开(公告)号：US20200043856A1

公开(公告)日：2020-02-06

申请号：US16519527

申请日：2019-07-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki OMORI

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device having a contact resistance lower than that of a conventional semiconductor device is provided. The semiconductor device comprises a conductive region arranged in or on the semiconductor substrate, an insulating film arranged on the conductive region and provided with a contact hole reaching from the second surface to the conductive region, and a contact plug arranged in contact hole and connected to the conductive region. The contact plug includes a first layer covering a side wall and a bottom wall of the contact hole, and a second layer arranged inside the first layer and located on the third surface of the contact plug in the contact hole. Materials constituting the first layer include aluminum and cobalt. The material constituting the second layer includes at least one of aluminum and copper and does not include cobalt.