公开(公告)号：US20240126472A1

公开(公告)日：2024-04-18

申请号：US18397851

申请日：2023-12-27

Applicant: Renesas Electronics Corporation

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20180277214A1

公开(公告)日：2018-09-27

申请号：US15900516

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi KURAFUJI ,  Tomoya OGAWA ,  Yasuhiko TAITO

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/0441 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/1063 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C2207/063

Abstract: A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.

公开(公告)号：US20220382483A1

公开(公告)日：2022-12-01

申请号：US17746437

申请日：2022-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20170047121A1

公开(公告)日：2017-02-16

申请号：US15167596

申请日：2016-05-27

Applicant: Renesas Electronics Corporation

Inventor： Masamichi FUJITO ,  Hiroshi YOSHIDA ,  Takanori TAKAHASHI ,  Yasuhiko TAITO

IPC: G11C16/20

CPC classification number: G11C16/20 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C16/3481

Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level.

Abstract translation: 半导体器件包括具有多个互补单元的存储器阵列，每个存储器阵列包括第一存储器元件和第二存储器元件，用于根据其间的阈值电压的差异来保持二进制数据，以及用于初始化互补单元的控制电路。 控制电路执行第一初始化控制，以减小互补单元的第一存储器元件和第二存储器元件的阈值电压，并将第一存储元件和第二存储元件中的至少一个的阈值电压改变为中间 低于第一写入电平并高于初始化电平的第一写入控制;改变第一写入电平时互补单元的第一存储器元件和第二存储器元件中的一个的阈值电压的第一写入控制;以及第二初始化控制 在初始化级别改变互补单元的第一存储元件和第二存储元件的阈值电压。