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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180102360A1

    公开(公告)日：2018-04-12

    申请号：US15835848

    申请日：2017-12-08

    Applicant: Renesas Electronics Corporation

    Inventor： Yasutaka NAKASHIBA ,  Yutaka AKIYAMA

    IPC: H01L27/06 ,  H01L23/522

    Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150060948A1

    公开(公告)日：2015-03-05

    申请号：US14472665

    申请日：2014-08-29

    Applicant: Renesas Electronics Corporation

    Inventor： Tohru KAWAI ,  Yutaka AKIYAMA ,  Yasutaka NAKASHIBA

    IPC: H01L29/778 ,  H01L29/205 ,  H01L29/201 ,  H01L29/40 ,  H01L29/20

    CPC classification number: H01L29/404 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

    Abstract: A field plate causes excessive gate capacitance that interferes with high-speed transistor switching. To suppress the excessive gate capacitance, an aperture includes a first side wall positioned on the side of a drain electrode, and a second side wall positioned on the side of a source electrode. A gate electrode at the same time includes a first side surface facing opposite the drain electrode as seen from a plan view. The first side surface of the gate electrode is positioned on the inner side of the first side wall and the second side wall as seen from a flat view. Moreover, a portion of a first field plate is embedded between the first side surface and the first side wall. The gate electrode and the first field plate are electrically insulated by a first insulation member.

    Abstract translation: 场板引起过大的栅极电容干扰高速晶体管切换。 为了抑制过剩的栅极电容，孔包括位于漏极侧的第一侧壁和位于源极侧的第二侧壁。 栅电极同时包括从俯视图看的与漏电极相对的第一侧表面。 从平面看，栅电极的第一侧表面位于第一侧壁和第二侧壁的内侧。 此外，第一场板的一部分嵌入在第一侧面和第一侧壁之间。 栅电极和第一场板由第一绝缘构件电绝缘。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150325696A1

    公开(公告)日：2015-11-12

    申请号：US14804819

    申请日：2015-07-21

    Applicant: Renesas Electronics Corporation

    Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

    CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

    Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

    Abstract translation: 一种半导体器件，包括第一导体层，形成在第一导体层上的第二导体层，形成在第二导体层上的第三导体层，通过第三导体层并形成在第二导体层中的栅极沟槽， 形成在栅极沟槽的内壁上的第一绝缘膜，形成在栅极沟槽的内壁上的第二绝缘膜，形成在栅极沟槽中的第一掩埋导体层，形成在栅极沟槽中的栅电极，第四绝缘膜 在第一掩埋导体层的下端形成的第二导电类型的导体层和栅极沟槽的下端，以及形成在第三导体层上的第一导电类型的第五导电层。 第一绝缘膜比第二绝缘膜厚。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140284709A1

    公开(公告)日：2014-09-25

    申请号：US14204145

    申请日：2014-03-11

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

    IPC: H01L29/78 ,  H01L29/423

    CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

    Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

    Abstract translation: 在漂移层中形成第二导电类型的掩埋层和第二导电类型的下层。 边界绝缘膜形成在第二导电类型的掩埋层的横向部分与漂移层之间的边界中。 第二导电类型的下层与第二导电类型的掩埋层的下端和边界绝缘膜的下端接触。 第二导电类型的掩埋层与源电极电连接。 在第二导电类型的掩埋层的表面层中形成第二导电类型的高浓度层。

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