公开(公告)号：US20130341727A1

公开(公告)日：2013-12-26

申请号：US13945282

申请日：2013-07-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro SHIMAMOTO ,  Jiro YUGAMI ,  Masao INOUE ,  Masaharu MIZUTANI

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.

Abstract translation: 公开了一种包括n沟道型的第一MISFET和ap沟道型的第二MISFET的半导体器件，每个MISFET被配置有具有硅氧化膜或氮氧化硅膜的栅极绝缘膜和包括 位于栅极绝缘膜上的导电硅膜。 金属元素如Hf在第一和第二MISFET中的栅电极和栅极绝缘膜之间的界面附近引入，使得表面密度为1×1013至5×1014原子/ cm2的金属原子包含在界面附近 并且第一和第二MISFET中的每一个具有含有浓度等于或低于1.2×1018 / cm3的杂质的沟道区。

公开(公告)号：US20160181147A1

公开(公告)日：2016-06-23

申请号：US15054696

申请日：2016-02-26

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

公开(公告)号：US20140131807A1

公开(公告)日：2014-05-15

申请号：US14157701

申请日：2014-01-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Jiro YUGAMI

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78

Abstract: A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET.

Abstract translation: 器件隔离区域由嵌入在沟槽中的氧化硅膜制成，其上部从半导体衬底突出，并且在器件的一部分的侧壁上形成由氮化硅或氮氧化硅制成的侧壁绝缘膜 隔离区域从半导体衬底突出。 MISFET的栅极绝缘膜由含有铪，氧和用于阈值还原的元素作为主要成分的含Hf绝缘膜制成，作为金属栅电极的栅电极在有源区上延伸，侧壁绝缘膜 和器件隔离区。 当MISFET为p沟道MISFET时，MISFET为n沟道MISFET时，用于阈值降低的元件为稀土或Mg，阈值降低元件为Al，Ti或Ta。

公开(公告)号：US20130140669A1

公开(公告)日：2013-06-06

申请号：US13691800

申请日：2012-12-02

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

Abstract translation: 在SOI衬底上形成作为半导体元件的第一MISFET。 SOI衬底包括作为基底的支撑衬底，BOX层，其是形成在支撑衬底的主表面（表面）上的绝缘层，即掩埋氧化物膜; 以及作为在BOX层上形成的半导体层的SOI层。 作为半导体元件的第一MISFET形成于SOI层。 在隔离区域中，穿过SOI层和BOX层形成隔离槽，使得槽的底面位于支撑基板的厚度的中间。 隔离膜被埋在正在形成的隔离槽中。 然后，在BOX层和隔离膜之间插入抗氧化膜。