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公开(公告)号：US20230402081A1
公开(公告)日：2023-12-14
申请号：US18313684
申请日：2023-05-08
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA
CPC classification number: G11C11/1697 , G11C5/08 , G11C7/06
Abstract: A semiconductor device capable of increasing readout margin in a nonvolatile resistive random access memory is provided. A clamping circuit applies fixed potential to each of a memory element and a reference resistive element. A pre-charge circuit pre-charges first and second nodes to power-source potential. A sense amplifier amplifies the potential difference between the potential of the first node and the potential of the second node generated after a discharge period based on cell current and reference current after pre-charging made by the pre-charge circuit. A third node is coupled to the first and second nodes through a capacitor. An electric-charge supply circuit is connected to the third node, and supplies electric charge to the third node in the discharge period.
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公开(公告)号：US20230145662A1
公开(公告)日：2023-05-11
申请号：US17965308
申请日：2022-10-13
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA , Takahiro SHIMOI , Masaya NAKANO , Hidenori MITANI , Yoshinobu KANEDA
IPC: H03F3/45
CPC classification number: H03F3/45744 , H03F3/45497 , H03F3/45511
Abstract: Speed enhancement of data reading is achieved while suppressing an influence of an offset voltage of a differential amplifier. The differential amplifier includes: a current source that is connected to a first power supply in which a suppliable current is a first current; an active element pair that is connected to the current source, and amplifies a signal input to an input terminal pair to output an output signal pair; a load element pair that is connected to a second power supply different in power supply voltage from the first power supply, the load element pair serving for outputting the output signal pair to an output terminal pair; and a capacitance element pair that is inserted between an external input terminal pair and the input terminal pair; a switching element pair that charges the capacitance element pair to generate a voltage, which is obtained by converting an offset voltage of the input terminal pair into an input voltage, in the capacitance element pair by short-circuiting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit that controls a current suppliable by the current source to a second current larger than the first current at a time of performing the charge.
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公开(公告)号：US20200327921A1
公开(公告)日：2020-10-15
申请号：US16828545
申请日：2020-03-24
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA
IPC: G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4094 , G11C11/4091
Abstract: A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.
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公开(公告)号：US20130259144A1
公开(公告)日：2013-10-03
申请号：US13784262
申请日：2013-03-04
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA , Shunichi KAERIYAMA
IPC: H04L25/02
CPC classification number: H04L25/026 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014 , H01L2924/13091 , H01L2924/30107 , H04L25/0266 , H01L2924/00 , H01L2224/45099
Abstract: A receiver includes a positive pulse determination circuit and a negative pulse determination circuit. The positive pulse determination circuit outputs a first L-level between when a pulse signal having a negative amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a first H-level if a pulse signal having a positive amplitude is detected during another period. The negative pulse determination circuit outputs a second L-level between when a pulse signal having a positive amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a second H-level is output if a pulse signal having a negative amplitude is detected during the other period.
Abstract translation: 接收机包括正脉冲确定电路和负脉冲确定电路。 正脉冲确定电路在检测到具有负幅度的脉冲信号之间并且既没有检测到具有正振幅的脉冲信号也没有检测到具有负幅度的脉冲信号时，输出第一L电平; 否则如果在另一周期期间检测到具有正振幅的脉冲信号，则第一H电平。 负脉冲判定电路在检测到具有正振幅的脉冲信号之间并且既没有检测到具有正振幅的脉冲信号也没有检测到具有负幅度的脉冲信号时，输出第二L电平; 否则如果在其他周期内检测到具有负幅度的脉冲信号，则输出第二H电平。
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公开(公告)号：US20190260360A1
公开(公告)日：2019-08-22
申请号：US16249502
申请日：2019-01-16
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA
IPC: H03K3/012 , H03K3/037 , H03K19/0185
Abstract: A level shift circuit includes a pulse signal generation unit generating first and second pulse signals with respect to an input signal, a first level conversion unit converting the first pulse signal at a first voltage to a third pulse signal at a second voltage, a second level conversion unit converting the second pulse signal at the first voltage to a fourth pulse signal at the second voltage, and a flip flop circuit making an output signal at the second voltage rise according to the third pulse signal, and making the output signal at the second voltage fall according to the fourth pulse signal. The pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal when the input signal rises and the second pulse signal when the input signal falls, based on a non-matching comparison result.
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Patent Agency Ranking
公开(公告)号：US20180302068A1
公开(公告)日：2018-10-18
申请号：US16013430
申请日：2018-06-20
Applicant: Renesas Electronics Corporation
Inventor： Hirokazu NAGASE , Koichi TAKEDA , Shunichi KAERIYAMA
IPC: H03K5/04
Abstract: To provide a receiver, a communication device, and a communication method capable of restoring a signal transmitted via a non-contact transmission channel with high accuracy. A communication device has a transmission circuit that converts an input signal into a pulse, a non-contact transmission channel that has a primary side coil and a secondary side coil and transmits the pulse from the transmission circuit in a non-contact manner, a restoration circuit that restores the input signal on the basis of a reception signal corresponding to the pulse transmitted via the non-contact transmission channel, an initialization unit that initializes an output of the non-contact transmission channel, and an initialization control unit that outputs a control signal of controlling the initialization unit on the basis of the reception signal corresponding to the pulse received via the non-contact transmission channel.
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公开(公告)号：US20160065214A1
公开(公告)日：2016-03-03
申请号：US14836805
申请日：2015-08-26
Applicant: Renesas Electronics Corporation
Inventor： Koichi TAKEDA
IPC: H03K19/00 , H03K19/20 , H03K19/0948
CPC classification number: H03K19/0013 , H03K19/0948 , H03K19/20
Abstract: According to one embodiment, a semiconductor device includes: an inverter gate circuit which inverts and outputs a logic level of an input signal, the inverter gate circuit includes a constant current source and a switch unit which are connected in series between a first power supply wiring and a second power supply wiring, and, according to the control signal, the switch unit switches real values of a gate length and a gate width of a switch transistor configured by a transistor to which a current outputted from the constant current source is applied among a plurality of transistors.
Abstract translation: 根据一个实施例，半导体器件包括：反相器门电路，其反相并输出输入信号的逻辑电平，反相器门电路包括恒流源和开关单元，串联连接在第一电源布线 和第二电源布线，并且根据控制信号，开关单元切换由施加从恒流源输出的电流的晶体管构成的开关晶体管的栅极长度和栅极宽度的实际值， 多个晶体管。
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8.发明申请公开(公告)号：US20190172503A1
公开(公告)日：2019-06-06
申请号：US16151089
申请日：2018-10-03
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA , Takashi IWASE
CPC classification number: G11C5/14 , G11C7/1093 , G11C8/08 , G11C8/10 , G11C8/14 , G11C8/18 , H03K5/1534 , H03K19/0185 , H03K19/018521
Abstract: According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.
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公开(公告)号：US20180041233A1
公开(公告)日：2018-02-08
申请号：US15727968
申请日：2017-10-09
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA , Hirokazu NAGASE , Shinpei WATANABE
CPC classification number: H04B1/04 , H01L23/60 , H01L2924/16152 , H04B1/40 , H04B5/0012 , H04B5/0075 , H04B5/0081 , H04L1/0041 , H04L25/0266
Abstract: The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.
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公开(公告)号：US20230402080A1
公开(公告)日：2023-12-14
申请号：US18317382
申请日：2023-05-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Koichi TAKEDA , Akihiko KANDA , Takahiro SHIMOI
CPC classification number: G11C11/1673 , G11C11/1675 , G11C7/08
Abstract: A clamp element 46 applies a fixed potential to a bit line BL at a time of a readout operation. A reference current source RCS generates a reference current Iref. An offset current source OCS1 is activated at a time of a readout operation for an OTP cell OTPC, and at a time of being activated, generates an offset current Iof1 to be subtracted from a cell current Icel. At the time of the readout operation for the OTP cell OTPC, the sense amplifier SA detects a magnitude relationship between the reference current Iref and a readout current Ird obtained by subtracting the offset current Iof1 from the cell current Icel.
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