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26 条记录 (耗时 0.017 秒)

    Distributed signal transmission to an integrated circuit array
    1.
    发明授权
    Distributed signal transmission to an integrated circuit array 失效
    分布式信号传输到集成电路阵列

    公开(公告)号：US4969123A

    公开(公告)日：1990-11-06

    申请号：US265112

    申请日：1988-10-31

    申请人： Roger D. Norwood ,  Jimmie D. Childers

    发明人： Roger D. Norwood ,  Jimmie D. Childers

    IPC分类号： G11C5/06 ,  G11C11/4091 ,  G11C11/4097

    CPC分类号： G11C11/4091 ,  G11C11/4097 ,  G11C5/063

    摘要： In a dynamic random access memory (10) that includes a cell array area (12) and at least one peripheral array area (14), a plurality of sense amplifier banks (20) are arranged in rows. A plurality of elongate longitudinal signal conductors (92) are formed over the cell array area (12) to intersect each of the rows. Each row has at least one transverse signal conductor (98) that is coupled to at least some of the longitudinal signal conductors (92). Inputs of the sense amplifiers (30) in the row are coupled to the transverse signal conductor (92) for receiving the global signal. A signal driver circuit (124-130) is formed in the peripheral area (14), with the longitudinal conductors (98) coupled to outputs of the signal driver circuit (124-130).

    摘要翻译： 在包括单元阵列区域（12）和至少一个外围阵列区域（14）的动态随机存取存储器（10）中，多个读出放大器组（20）被排列成行。 多个细长纵向信号导体（92）形成在单元阵列区域（12）上以与每行相交。 每排具有至少一个横向信号导体（98），其耦合到至少一些纵向信号导体（92）。 行中的读出放大器（30）的输入耦合到横向信号导体（92），用于接收全局信号。 信号驱动器电路（124-130）形成在周边区域（14）中，纵向导体（98）耦合到信号驱动电路（124-130）的输出端。

    Glitch suppression circuit
    2.
    发明授权
    Glitch suppression circuit 失效
    毛刺抑制电路

    公开(公告)号：US4965474A

    公开(公告)日：1990-10-23

    申请号：US486621

    申请日：1990-02-26

    申请人： Jimmie D. Childers ,  Roger D. Norwood

    发明人： Jimmie D. Childers ,  Roger D. Norwood

    IPC分类号： G11C11/4076 ,  H03K5/1534 ,  H03K19/003

    CPC分类号： G11C11/4076 ,  H03K19/00346 ,  H03K5/1534

    摘要： The described embodiment of the present invention includes a combinatorial circuit, such as a multiplexor. All or a portion of the input signals to the multiplexor are also provided to a transition detector. Upon detecting a transition, the transition detector provides a signal which temporarily suppresses the operation of the combinatorial circuit prior to a portion of the combinatorial circuit which is sensitive to glitches and/or timing errors. The delay allows time for glitches and/or timing errors to dissipate. This provides a cleaner signal for the sensitive portion to avoid the errors that the suppressed glitches and/or timing errors may cause.

    摘要翻译： 本发明的所描述的实施例包括诸如多路复用器的组合电路。 向多路复用器的输入信号的全部或一部分也被提供给转换检测器。 在检测到转变时，转换检测器提供一个信号，该信号在对毛刺和/或定时误差敏感的组合电路的一部分之前临时抑制组合电路的操作。 延迟允许时间毛刺和/或定时错误消散。 这为敏感部分提供了更清洁的信号，以避免抑制的毛刺和/或定时误差可能导致的错误。

    Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode
    5.
    发明授权
    Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode 失效
    半导体动态存储器件，具有页面模式或半字节模式的金属级选择

    公开(公告)号：US4876671A

    公开(公告)日：1989-10-24

    申请号：US336637

    申请日：1989-04-06

    申请人： Roger D. Norwood ,  Jino Chun ,  Pravin P. Patel

    发明人： Roger D. Norwood ,  Jino Chun ,  Pravin P. Patel

    IPC分类号： G11C11/4096

    CPC分类号： G11C11/4096

    摘要： A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the column strobe or CAS input by conductor, so this clock voltage is rendered either dependent on, or independent of, the cycling of the column strobe.

    摘要翻译： 公开了一种半导体动态存储器件，其包含使用导体电平选择来实现页模式和半字节模式的电路。 在列解码和输出中使用的时钟电压或者与列选通或由输入的CAS输入耦合或分离，因此该时钟电压取决于或不依赖于列选通的循环。

    Interface level programmability
    7.
    发明授权
    Interface level programmability 失效
    接口级可编程性

    公开(公告)号：US5557219A

    公开(公告)日：1996-09-17

    申请号：US456436

    申请日：1995-06-01

    申请人： Roger D. Norwood ,  Brian L. Brown

    发明人： Roger D. Norwood ,  Brian L. Brown

    IPC分类号： H03K19/0185 ,  H03K19/173

    CPC分类号： H03K19/018585

    摘要： A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.

    摘要翻译： 接口电路（15,20-1至20-N）的系统包括模式感测电路（15）和一个或多个输出电路（20-1至20-N）。 模式感测电路被布置成响应于输入信号（在引线21上）产生控制信号（在引线22,24上）。 输出电路（34-1）被布置用于当输入信号（在引线21上）处于第一状态并且取决于输入数据时，根据输入数据信号（DATA）产生输出数据信号（DQ-1） 信号以及当输入信号处于第二状态时连接的输出电路（34-1）的配置。

    Semiconductor dynamic memory device with multiplexed sense amplifier and write-activated active loads
    8.
    发明授权
    Semiconductor dynamic memory device with multiplexed sense amplifier and write-activated active loads 失效
    半导体动态存储器件具有多路复用读出放大器和写激活的有源负载

    公开(公告)号：US4636987A

    公开(公告)日：1987-01-13

    申请号：US645581

    申请日：1984-08-29

    申请人： Roger D. Norwood ,  Chitranjan Reddy

    发明人： Roger D. Norwood ,  Chitranjan Reddy

    IPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C7/02

    CPC分类号： G11C11/4094 ,  G11C11/4096

    摘要： A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit line halves which are of the folded type. The sense amplifiers are multiplexed so that one of two opposite pairs of bit line halves are selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. Thus, the multiplex circuitry operates not only for selecting one side or the other for sensing, but also for coupling precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other. The active pull-up circuits are activated in both read and write portions of a read-modify-write cycle.

    摘要翻译： 半导体动态存储器件包含差分读出放大器，用于检测折叠型的位线半部上的电荷。 读出放大器被复用，使得选择两个相对的位线对中的一个。 两个相对的对在阵列的一侧共享预充电和有源上拉电路，并在相对侧共享列输出线。 因此，多路复用电路不仅用于选择一侧或另一侧用于感测，而且用于将预充电和升压电压或从读出放大器的一侧来回读取/写入数据到另一侧。 激活的上拉电路在读 - 修改 - 写周期的读和写部分都被激活。

    Method and apparatus for inhibiting a predecoder when selecting a redundant row line
    9.
    发明授权
    Method and apparatus for inhibiting a predecoder when selecting a redundant row line 失效
    在选择冗余行线时禁止预解码器的方法和装置

    公开(公告)号：US5475640A

    公开(公告)日：1995-12-12

    申请号：US215554

    申请日：1994-03-21

    申请人： David V. Kersh, III ,  Roger D. Norwood

    发明人： David V. Kersh, III ,  Roger D. Norwood

    IPC分类号： G11C29/00 ,  G11C8/00

    CPC分类号： G11C29/787

    摘要： A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWL1L). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

    摘要翻译： 提供一种用于用冗余信号路径（95,96）代替多个类似信号路径的有缺陷信号路径（94）的电路。 冗余解码器（72）可编程为响应正常操作以解决缺陷信号路径（94，ROWL1R和ROWL1L）的多个预定寻址信号（RFn）。 冗余解码器可操作以响应于预定寻址信号（RFn）产生禁用信号（RREN），并且还可操作以响应于此选择冗余信号路径（95,96）。 解码电路（70,74）通常解码多个寻址信号（RFn）中的选定的寻址信号（RFn），并响应于此选择多个信号路径中的至少一个。 解码电路（70,74）耦合到冗余解码器（72），用于从其中接收禁用信号（RREN）。 响应于接收到该禁用信号（RREN），解码电路（70,74）将不解码预选的寻址信号（RFn）。