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    SEMICONDUCTOR DEVICES
    2.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190325960A1

    公开(公告)日：2019-10-24

    申请号：US16458594

    申请日：2019-07-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNGWOO KIM ,  BONG-SOO KIM ,  YOUNGBAE KIM ,  KIJAE HUR ,  GWANHYEOB KOH ,  HYEONGSUN HONG ,  YOOSANG HWANG

    IPC: G11C14/00 ,  H01L45/00 ,  G11C5/02 ,  G11C13/00 ,  G11C11/00 ,  H01L23/528 ,  H01L27/24

    Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210125998A1

    公开(公告)日：2021-04-29

    申请号：US16990305

    申请日：2020-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEOK-HYUN KIM ,  Joon Young KANG ,  YOUNGJUN KIM ,  JINHYUNG PARK ,  HO-JU SONG ,  SANG-JUN LEE ,  HYERAN LEE ,  BONG-SOO KIM ,  SUNGWOO KIM

    IPC: H01L27/108

    Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

    SEMICONDUCTOR DEVICES
    5.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190325930A1

    公开(公告)日：2019-10-24

    申请号：US16460284

    申请日：2019-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNGWOO KIM ,  BONG-SOO KIM ,  YOUNGBAE KIM ,  KIJAE HUR ,  GWANHYEOB KOH ,  HYEONGSUN HONG ,  YOOSANG HWANG

    IPC: G11C11/00 ,  G11C5/02 ,  G11C14/00 ,  H01L27/108 ,  H01L23/528 ,  H01L27/24 ,  H01L49/02 ,  H01L45/00

    Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

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