公开(公告)号：US10134713B2

公开(公告)日：2018-11-20

申请号：US15815042

申请日：2017-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-seok Kim ,  Sun-won Kang ,  Il-joon Kim

IPC: H01L25/065 ,  H01L23/64 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.

公开(公告)号：US09355947B2

公开(公告)日：2016-05-31

申请号：US14698826

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-soon Kang ,  Sun-won Kang ,  Joon-young Park ,  Doo-hee Hwang ,  Tae-young Yoon

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85423 ,  H01L2224/85447 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group.

Abstract translation: 印刷电路板（PCB）包括：基底基板，包括上表面和下表面;多个焊球焊盘，其分别形成在基底基板的下表面上并沿径向形成一个或多个径向焊盘组;多个第一 分别连接到多个焊球焊盘并延伸到径向焊盘组的内部的迹线以及分别连接到多个第一迹线并延伸到径向焊盘组的外部的多个第二迹线。

公开(公告)号：US20130292846A1

公开(公告)日：2013-11-07

申请号：US13768649

申请日：2013-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-hyun Lee ,  Sun-won Kang ,  Ho-geon Song

IPC: H01L23/538

CPC classification number: H01L23/538 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: Provided is a semiconductor package including a first semiconductor chip and a second semiconductor chip respectively disposed at a bottom and at a top so that active surfaces thereof face each other. Further includes is a first molding member for sealing the first semiconductor chip and exposing the active surface of the first semiconductor chip through a top surface, a first rewiring formed on the top surface of the first molding member and the active surface of the first semiconductor chip, a second rewiring formed on a bottom surface of the first molding member, a through-via for penetrating through the first molding member and electrically connecting the first and second rewirings, and a first connection member disposed between the first and second semiconductor chips. Also provided are various systems including same and various methods for making same.

Abstract translation: 提供了一种半导体封装，其包括分别设置在底部和顶部的第一半导体芯片和第二半导体芯片，使得其有效表面彼此面对。 还包括第一模制构件，用于密封第一半导体芯片并通过顶表面暴露第一半导体芯片的活性表面，第一重新布线形成在第一模制构件的顶表面上，第一半导体芯片的有源表面 ，形成在第一成型构件的底面上的第二重新布线，穿过第一成型构件并电连接第一和第二重新布置的通孔，以及设置在第一和第二半导体芯片之间的第一连接构件。 还提供了包括相同的各种系统和用于制造它们的各种方法。

公开(公告)号：US10141293B2

公开(公告)日：2018-11-27

申请号：US15857882

申请日：2017-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-hong Kwon ,  Sang-nam Jeong ,  Sun-won Kang ,  Hee-jin Lee

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.

公开(公告)号：US09859263B2

公开(公告)日：2018-01-02

申请号：US15239020

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-hong Kwon ,  Sang-nam Jeong ,  Sun-won Kang ,  Hee-jin Lee

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.