公开(公告)号：US20180350445A1

公开(公告)日：2018-12-06

申请号：US15610119

申请日：2017-05-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Shantanu Gupta ,  Avinash Rajagiri ,  Dongxiang Liao ,  Jagdish Sabde ,  Rajan Paudel

IPC: G11C29/12 ,  G11C7/10

CPC classification number: G11C29/1201 ,  G11C7/10 ,  G11C7/22

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

公开(公告)号：US11475957B2

公开(公告)日：2022-10-18

申请号：US17149560

申请日：2021-01-14

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Dongxiang Liao ,  Jiahui Yuan

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatuses and techniques are described for optimizing programming in a memory device in which memory cells can be programmed using single bit per cell programming and multiple bits per cell programming. In one aspect, a single bit per cell program operation is performed which reduces damage to the memory cells as well as reducing program time. The program operation can omit a pre-charge phase and a verify phase of an initial program loop of a program operation. Instead, a program phase is performed followed by a recovery phase. In one or more subsequent program loops of the single bit per cell program operation, as well as in each program loop of a multiple bit per cell program operation, the program loop includes a pre-charge phase, a program phase, a recovery phase and a verify phase.

公开(公告)号：US10991447B2

公开(公告)日：2021-04-27

申请号：US16451421

申请日：2019-06-25

Applicant: SanDisk Technologies LLC

Inventor： Daniel Linnen ,  Avinash Rajagiri ,  Dongxiang Liao ,  Kirubakaran Periyannan

IPC: G11C29/56 ,  G06F11/16 ,  G11C16/32 ,  G11C5/14

Abstract: A method for detecting faults in a memory system includes performing an operation on at least one memory cell of the memory system. The method also includes receiving, during performance of the operation, a first clock cycle count for a first pulse of a charge pump associated with the at least one memory cell. The method also includes receiving, during performance of the operation, a second clock cycle count for a second pulse of the charge pump. The method also includes determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.

公开(公告)号：US10886002B1

公开(公告)日：2021-01-05

申请号：US16440212

申请日：2019-06-13

Applicant: SanDisk Technologies LLC

Inventor： Daniel Linnen ,  Avinash Rajagiri ,  Yuvaraj Krishnamoorthy ,  Srikar Peesari ,  Ashish Ghai ,  Dongxiang Liao

IPC: G11C29/38 ,  G06F13/16 ,  G11C16/04 ,  G11C16/14 ,  G11C29/44

Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

公开(公告)号：US20220223209A1

公开(公告)日：2022-07-14

申请号：US17149560

申请日：2021-01-14

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Dongxiang Liao ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C11/56

Abstract: Apparatuses and techniques are described for optimizing programming in a memory device in which memory cells can be programmed using single bit per cell programming and multiple bits per cell programming. In one aspect, a single bit per cell program operation is performed which reduces damage to the memory cells as well as reducing program time. The program operation can omit a pre-charge phase and a verify phase of an initial program loop of a program operation. Instead, a program phase is performed followed by a recovery phase. In one or more subsequent program loops of the single bit per cell program operation, as well as in each program loop of a multiple bit per cell program operation, the program loop includes a pre-charge phase, a program phase, a recovery phase and a verify phase.

公开(公告)号：US10242750B2

公开(公告)日：2019-03-26

申请号：US15610119

申请日：2017-05-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Linnen ,  Srikar Peesari ,  Kirubakaran Periyannan ,  Shantanu Gupta ,  Avinash Rajagiri ,  Dongxiang Liao ,  Jagdish Sabde ,  Rajan Paudel

IPC: G11C29/12 ,  G11C7/10 ,  G11C7/22

Abstract: Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.