公开(公告)号：US11222881B2

公开(公告)日：2022-01-11

申请号：US16900486

申请日：2020-06-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Kwang-Ho Kim ,  Johann Alsmeier

IPC: G11C16/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

公开(公告)号：US10910064B2

公开(公告)日：2021-02-02

申请号：US16400280

申请日：2019-05-01

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/32 ,  G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  H01L27/11582 ,  H01L27/11556

Abstract: An apparatus comprising strings of non-volatile memory cells, a first set of pathways connected to the strings, and a second set of pathways connected to the strings. The first set of pathways have first impedances that depend on location of respective strings. The second set of pathways having second impedances. The apparatus also includes one or more control circuits configured to compensate for location dependent impedance mismatch between the first set of pathways and the second set of pathways during memory operations on the non-volatile memory cells.

公开(公告)号：US10861873B2

公开(公告)日：2020-12-08

申请号：US16404844

申请日：2019-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon Kim ,  Kwang-Ho Kim ,  Fumiaki Toyama

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11529 ,  G11C5/06 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions. Metal line structures connecting contact via structures can extend parallel to bit lines to provide electrical connections between word lines and underlying field effect transistors.

公开(公告)号：US11031308B2

公开(公告)日：2021-06-08

申请号：US16426984

申请日：2019-05-30

Applicant: SanDisk Technologies LLC

Inventor： Seungpil Lee ,  Kwang-Ho Kim

IPC: H01L25/18 ,  H01L21/66 ,  H01L27/11582 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  G01R31/50

Abstract: A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad.

公开(公告)号：US20200343235A1

公开(公告)日：2020-10-29

申请号：US16900486

申请日：2020-06-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Kwang-Ho Kim ,  Johann Alsmeier

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11573 ,  H01L25/065 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  G11C16/04 ,  H01L23/48

Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

公开(公告)号：US10755788B2

公开(公告)日：2020-08-25

申请号：US16233780

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11524

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

公开(公告)号：US10748894B2

公开(公告)日：2020-08-18

申请号：US16251954

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murshed Chowdhury ,  Kwang-Ho Kim ,  James Kai ,  Johann Alsmeier

IPC: G11C15/00 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11529 ,  G11C5/02 ,  H01L23/48 ,  H01L23/00 ,  H01L27/1157

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.

公开(公告)号：US11296113B2

公开(公告)日：2022-04-05

申请号：US17007761

申请日：2020-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Peter Rabkin

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11565 ,  H01L27/11556

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US11791327B2

公开(公告)日：2023-10-17

申请号：US17411635

申请日：2021-08-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Masaaki Higashitani ,  Fumiaki Toyama ,  Akio Nishida

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/48 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/481 ,  H01L23/5226 ,  H01L2224/08145 ,  H01L2224/8083 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US11569215B2

公开(公告)日：2023-01-31

申请号：US17007823

申请日：2020-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Peter Rabkin

IPC: H01L25/18 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.