Non-volatile memory with adapting erase process

    公开(公告)号:US12147695B2

    公开(公告)日:2024-11-19

    申请号:US18358661

    申请日:2023-07-25

    Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

    Non-volatile memory with optimized operation sequence

    公开(公告)号:US12153801B2

    公开(公告)日:2024-11-26

    申请号:US17983870

    申请日:2022-11-09

    Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

    EARLY PROGRAM TERMINATION WITH ADAPTIVE TEMPERATURE COMPENSATION

    公开(公告)号:US20240168661A1

    公开(公告)日:2024-05-23

    申请号:US18355337

    申请日:2023-07-19

    Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.

    Smart erase scheme
    9.
    发明授权

    公开(公告)号:US11355198B1

    公开(公告)日:2022-06-07

    申请号:US17152435

    申请日:2021-01-19

    Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.

    HOLE PRE-CHARGE SCHEME USING GATE INDUCED DRAIN LEAKAGE GENERATION

    公开(公告)号:US20210408024A1

    公开(公告)日:2021-12-30

    申请号:US16916186

    申请日:2020-06-30

    Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

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