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公开(公告)号：US12147695B2
公开(公告)日：2024-11-19
申请号：US18358661
申请日：2023-07-25
Applicant: SanDisk Technologies LLC
Inventor： Longju Liu , Yi Song , Sarath Puthenthermadam , Jiahui Yuan
IPC: G06F3/06
Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.
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公开(公告)号：US11972801B2
公开(公告)日：2024-04-30
申请号：US17665824
申请日：2022-02-07
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Yu-Chung Lien , Sarath Puthenthermadam , Sujjatul Islam
Abstract: A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.
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公开(公告)号：US20180182463A1
公开(公告)日：2018-06-28
申请号：US15391006
申请日：2016-12-27
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Deepanshu Dutta , Sarath Puthenthermadam , Chris Yip
CPC classification number: G11C16/3427 , G06F3/0619 , G06F3/0626 , G06F3/0658 , G06F3/0679 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3459
Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.
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公开(公告)号：US09805809B1
公开(公告)日：2017-10-31
申请号：US15253864
申请日：2016-08-31
Applicant: SanDisk Technologies LLC
Inventor： Zhenming Zhou , Guirong Liang , Gerrit Jan Hemink , Dana Lee , Chandu Gorla , Sarath Puthenthermadam , Deepanshu Dutta
CPC classification number: G11C16/26 , G11C16/0433 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3427
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells comprising a plurality of word lines. A controller is configured to perform a read operation on one or more word lines adjacent to a target word line. A controller is configured to determine a read setting for application to a target word line based on a result of a read operation on one or more word lines adjacent to the target word line. A controller is configured to perform a read operation on a target word line using a determined read setting.
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公开(公告)号：US09721652B2
公开(公告)日：2017-08-01
申请号：US15354446
申请日：2016-11-17
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Deepanshu Dutta
CPC classification number: G11C11/5642 , G11C11/5628 , G11C11/5635 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3427 , G11C16/3459
Abstract: A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower threshold voltages. A compensation pass bias can be reduced as the state being sensed at a selected word line increases to account for the different effects. A compensation pass bias for an adjacent word line may be reduced with the application of larger read reference voltages to a selected word line. Other variations to a compensation pass bias are provided.
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Patent Agency Ranking
公开(公告)号：US12153801B2
公开(公告)日：2024-11-26
申请号：US17983870
申请日：2022-11-09
Applicant: SanDisk Technologies LLC
Inventor： Yihang Liu , Xiaochen Zhu , Jie Liu , Sarath Puthenthermadam , Jiahui Yuan , Feng Gao
Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.
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公开(公告)号：US20240168661A1
公开(公告)日：2024-05-23
申请号：US18355337
申请日：2023-07-19
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Yihang Liu , Jiahui Yuan
CPC classification number: G06F3/0629 , G06F3/0619 , G06F3/0679 , G11C29/12005 , G11C2029/1202
Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.
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公开(公告)号：US20230253049A1
公开(公告)日：2023-08-10
申请号：US17666810
申请日：2022-02-08
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Deepanshu Dutta , Sarath Puthenthermadam , Jiahui Yuan
CPC classification number: G11C16/102 , G11C16/26 , G11C16/08 , G11C16/24 , G11C16/30
Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.
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公开(公告)号：US11355198B1
公开(公告)日：2022-06-07
申请号：US17152435
申请日：2021-01-19
Applicant: SanDisk Technologies LLC
Inventor： Fanqi Wu , Huai-Yuan Tseng , Sarath Puthenthermadam
IPC: G11C16/34 , G11C16/14 , G11C16/04 , G11C16/08 , H01L27/11565 , H01L27/11582 , G11C16/26 , H01L27/11519 , H01L27/11556
Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.
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公开(公告)号：US20210408024A1
公开(公告)日：2021-12-30
申请号：US16916186
申请日：2020-06-30
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Yanli Zhang , Huai-yuan Tseng , Peng Zhang
IPC: H01L27/11556 , G11C5/02 , G11C5/06 , H01L29/06 , H01L27/11582
Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.
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