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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250008748A1

    公开(公告)日：2025-01-02

    申请号：US18885848

    申请日：2024-09-16

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

    IPC: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

    Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
    [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220180920A1

    公开(公告)日：2022-06-09

    申请号：US17439876

    申请日：2020-03-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Seiya SAITO ,  Yuto YAKUBO ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

    IPC: G11C11/4097 ,  G11C11/4091 ,  H01L27/108 ,  H01L29/786

    Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.

    MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
    5.
    发明申请
    MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20220108985A1

    公开(公告)日：2022-04-07

    申请号：US17424664

    申请日：2019-11-22

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Takahiko ISHIZU ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

    IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

    Abstract: A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210398988A1

    公开(公告)日：2021-12-23

    申请号：US17466442

    申请日：2021-09-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

    IPC: H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

    Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
    [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-lth sub memory cell.

    SEMICONDUCTOR MATERIAL AND SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR MATERIAL AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210036025A1

    公开(公告)日：2021-02-04

    申请号：US16964115

    申请日：2019-01-17

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Hitoshi KUNITAKE ,  Shuhei NAGATSUKA

    IPC: H01L27/12 ,  H01L27/13

    Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, or dielectric breakdown is inhibited is provided. A first transistor, a second transistor, a third transistor, and a fourth transistor are included over a substrate; the fourth transistor includes a first conductor, a second conductor, a third conductor, and an oxide semiconductor; the first conductor is electrically connected to the semiconductor substrate through the first transistor; the second conductor is electrically connected to the semiconductor substrate through the first transistor; the third conductor is electrically connected to the semiconductor substrate through the first transistor; and the fourth conductor is electrically connected to the semiconductor substrate through the first transistor.

    ELECTRIC POWER CHARGE AND DISCHARGE SYSTEM
    8.
    发明申请
    ELECTRIC POWER CHARGE AND DISCHARGE SYSTEM 审中-公开

    公开(公告)号：US20200350786A1

    公开(公告)日：2020-11-05

    申请号：US16876082

    申请日：2020-05-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shuhei NAGATSUKA ,  Akihiro KIMURA

    IPC: H02J50/40 ,  H02J50/10 ,  H02J50/27 ,  H01M10/44 ,  H04B1/3883 ,  H02J7/00

    Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

    MEMORY DEVICE
    9.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20200343244A1

    公开(公告)日：2020-10-29

    申请号：US16757025

    申请日：2018-11-19

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hisao IKEDA ,  Shuhei NAGATSUKA

    IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

    Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200006328A1

    公开(公告)日：2020-01-02

    申请号：US16483302

    申请日：2018-01-31

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Shinya SASAGAWA ,  Shuhei NAGATSUKA

    IPC: H01L27/07 ,  H01L29/786

    Abstract: A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a fourth region with the first region and the second region provided therebetween, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, and a second conductor over the second region with the third insulator provided therebetween. A part of the third insulator is positioned between the second conductor and the side surface of the second insulator.

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