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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240130101A1

    公开(公告)日：2024-04-18

    申请号：US18485385

    申请日：2023-10-12

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Takanori MATSUZAKI ,  Toshihiko SAITO ,  Shunpei YAMAZAKI

    IPC: H10B12/00

    CPC classification number: H10B12/00 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor, a capacitor, and a first insulating layer. The first insulating layer is provided over a first conductive layer and a second conductive layer and includes a first opening reaching the first conductive layer and a second opening reaching the second conductive layer. The transistor is a vertical transistor in which a channel formation region is provided along the side wall of the first opening. The capacitor is a vertical capacitor in which a pair of electrodes and a dielectric are provided along the side surface of the second opening.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150014685A1

    公开(公告)日：2015-01-15

    申请号：US14500445

    申请日：2014-09-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

    IPC: H01L27/12

    CPC classification number: H01L27/124 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/40

    Abstract: An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

    Abstract translation: 目的是使半导体器件小型化。 另一个目的是减小包括存储单元的半导体器件的驱动电路的面积。 半导体器件包括至少设置有第一半导体元件的元件形成层，设置在元件形成层上的第一布线，设置在第一布线上的中间膜，和与第一布线重叠的第二布线，设置有夹层膜 之间。 第一布线，层间膜和第二布线包括在第二半导体元件中。 第一布线和第二布线是提供相同电位的布线。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20130181216A1

    公开(公告)日：2013-07-18

    申请号：US13795244

    申请日：2013-03-12

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Toshihiko SAITO ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Hiroki INOUE

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/0416 ,  G11C2211/4065 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

    Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

    Abstract translation: 一种半导体器件包括多个包括第一晶体管和第二晶体管的存储单元，包括放大器电路和开关元件的读取电路以及刷新控制电路。 第一通道形成区域和第二通道形成区域包含不同的材料作为它们各自的主要成分。 第一栅电极电连接到第二源电极和第二漏极之一。 第二源极和第二漏极中的另一个电连接到放大器电路的一个输入端。 放大器电路的输出端子通过开关元件连接到第二源电极和第二漏电极中的另一个。 刷新控制电路被配置为控制开关元件是打开还是关闭。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250133906A1

    公开(公告)日：2025-04-24

    申请号：US18574564

    申请日：2022-07-08

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Hidetomo KOBAYASHI ,  Yuki OKAMOTO ,  Toshihiko SAITO ,  Tatsuya ONUKI ,  Hidekazu MIYAIRI ,  Ryo TAGASHIRA ,  Kazuko YAMAWAKI ,  Masami ENDO

    IPC: H10K59/121 ,  G09G3/3233 ,  H10K59/131

    Abstract: A semiconductor device with high manufacturing yield is provided. The semiconductor device includes a plurality of subpixels. Each of the subpixels includes a first transistor, a second transistor, a first capacitor to a third capacitor, a first insulating layer, and a wiring. Each of the first capacitor to the third capacitor includes a first conductive layer, a second conductive layer, and a second insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer is provided over the first transistor and the second transistor. The first conductive layers of the first capacitor to the third capacitor and the wiring are each provided over the first insulating layer. In a top view, the proportion of the total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to the area of the subpixel is greater than or equal to 15 percent. The area of the first conductive layer of the second capacitor and the area of the first conductive layer of the third capacitor are each greater than or equal to twice the area of the first conductive layer of the first capacitor.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20140332809A1

    公开(公告)日：2014-11-13

    申请号：US14445515

    申请日：2014-07-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO ,  Kiyoshi KATO ,  Atsuo ISOBE

    IPC: H01L27/06 ,  H01L29/786 ,  H01L29/40 ,  H01L29/78

    CPC classification number: H01L27/0688 ,  G11C16/0433 ,  H01L21/02565 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78696

    Abstract: With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.

    Abstract translation: 通过包括氧化物半导体材料的晶体管和包括除了氧化物半导体之外的半导体材料的晶体管的组合，具有可以长时间保持数据并且对数字没有限制的新颖结构的半导体器件 的写作可以获得。 当用于将包括氧化物半导体的半导体材料的晶体管连接到包括氧化物半导体材料的晶体管的连接电极小于包含与连接电极连接的氧化物半导体以外的半导体材料的晶体管的电极时， 具有新颖结构的半导体器件可以高度集成，并且可以增加每单位面积的存储容量。

    MEMORY DEVICE AND ELECTRONIC DEVICE
    9.
    发明申请
    MEMORY DEVICE AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20230005528A1

    公开(公告)日：2023-01-05

    申请号：US17940065

    申请日：2022-09-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takahiko ISHIZU ,  Toshihiko SAITO ,  Hideki UOCHI ,  Shunpei YAMAZAKI

    IPC: G11C11/419 ,  G11C11/409 ,  H01L29/04 ,  H01L29/786

    Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160190149A1

    公开(公告)日：2016-06-30

    申请号：US15063874

    申请日：2016-03-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO

    IPC: H01L27/115 ,  H01L29/24 ,  H01L29/06 ,  H01L29/788 ,  H01L29/423

    CPC classification number: H01L27/1052 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/0649 ,  H01L29/247 ,  H01L29/42328 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/788

    Abstract: At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

    Abstract translation: 高度集成在元件中的多个晶体管中的至少一个设置有后栅，而不增加制造步骤的数量。 在包括纵向层叠的多个晶体管的元件中，上部的至少一个晶体管包括具有半导体特性的金属氧化物，与下部晶体管的栅电极相同的层被设置为与沟道重叠 上部的晶体管的形成区域和与栅极电极相同的层的一部分用作上部晶体管的背栅极。 被覆盖有绝缘层的下部的晶体管进行平坦化处理，从而使栅电极暴露并连接到作为上部晶体管的源电极和漏电极的层。

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