公开(公告)号：US10453996B2

公开(公告)日：2019-10-22

申请号：US15374547

申请日：2016-12-09

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L29/778 ,  H01L33/32 ,  H01L21/02 ,  H01L21/78 ,  H01L33/00 ,  H01L33/04 ,  H01L33/18 ,  H01L29/04

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

公开(公告)号：US20190103481A1

公开(公告)日：2019-04-04

申请号：US16191197

申请日：2018-11-14

Applicant: STC.UNM

Inventor： Steven R.J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02 ,  H01S5/32 ,  H01L29/04 ,  H01L29/66 ,  H01L29/423 ,  H01L29/205 ,  H01S5/343 ,  H01L33/00 ,  H01S5/02 ,  H01L33/24 ,  H01L29/40 ,  H01S5/227 ,  H01S5/22 ,  H01L33/32

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

公开(公告)号：US20170194476A1

公开(公告)日：2017-07-06

申请号：US15466461

申请日：2017-03-22

Applicant: STC.UNM

Inventor： Steven R.J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/205 ,  H01L29/04 ,  H01L21/306

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/02609 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/78 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/24 ,  H01L33/32 ,  H01S5/021 ,  H01S5/22 ,  H01S5/227 ,  H01S5/3203 ,  H01S5/34333

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

公开(公告)号：US20170092485A1

公开(公告)日：2017-03-30

申请号：US15374547

申请日：2016-12-09

Applicant: STC.UNM

Inventor： Steven R.J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L33/18 ,  H01L29/04 ,  H01L21/78 ,  H01L33/04

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

公开(公告)号：US20200006597A1

公开(公告)日：2020-01-02

申请号：US16567535

申请日：2019-09-11

Applicant: STC.UNM

Inventor： Steven R.J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L33/32 ,  H01L21/02 ,  H01L21/78 ,  H01L33/00 ,  H01L33/04 ,  H01L33/18 ,  H01L29/04

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

公开(公告)号：US10164082B2

公开(公告)日：2018-12-25

申请号：US15466461

申请日：2017-03-22

Applicant: STC.UNM

Inventor： Steven R. J. Brueck ,  Seung-Chang Lee ,  Christian Wetzel ,  Mark Durniak

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/205 ,  H01L29/08 ,  H01L21/78 ,  H01L29/04 ,  H01L29/423 ,  H01L29/06 ,  H01L33/00 ,  H01L33/32 ,  H01L29/40 ,  H01L33/24

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.