公开(公告)号：US10170475B2

公开(公告)日：2019-01-01

申请号：US15448626

申请日：2017-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Stephane Allegret-Maret ,  Kangguo Cheng ,  Bruce Doris ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L27/092 ,  H01L27/11 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US09893147B2

公开(公告)日：2018-02-13

申请号：US15345250

申请日：2016-11-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/01 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/16 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

公开(公告)号：US09502292B2

公开(公告)日：2016-11-22

申请号：US14856949

申请日：2015-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/20 ,  H01L21/425 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09099570B2

公开(公告)日：2015-08-04

申请号：US14097556

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/76205 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed.

Abstract translation: 在由第一半导体材料形成的衬底上沉积由第二半导体材料形成的第一覆盖层。 由第三半导体材料形成的第二覆盖层沉积在第一覆盖层上。 图案化第一和第二覆盖层以限定翅片，其中每个翅片包括在由第二材料形成的第二区域上由第三材料形成的第一区域。 氧化物填充翅片之间的空间。 然后进行热氧化以将第二区域转换为将由第三材料形成的第一区域与衬底绝缘的材料。 作为可选步骤，在沉积氧化物材料并进行热氧化之前，由第二材料形成的第二区域被水平地薄化。 一旦翅片形成并与衬底绝缘，就进行常规的FinFET制造。

公开(公告)号：US20150093861A1

公开(公告)日：2015-04-02

申请号：US14042884

申请日：2013-10-01

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L21/84

CPC classification number: H01L21/84

Abstract: An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.

Abstract translation: SOI衬底包括由STI结构分离并且包括栅叠层的第一和第二有源区。 在包括栅极堆叠的第一和第二区域上共形沉积的间隔层被定向蚀刻以沿着栅极堆叠的侧面限定侧壁间隔物。 然后沉积氧化物层和氮化物层。 使用掩模，去除第一有源区上的氮化物层，去除掩模和氧化物层以暴露第一有源区中的SOI衬底。 然后在第一有源区中与栅叠层相邻地外延生长凸起的源极 - 漏极结构，并且沉积保护性氮化物层。 然后重复掩模，氮化物层去除和氧化物层去除步骤以暴露第二有源区域中的SOI。 然后在第二活性区域中与栅叠层相邻地外延生长凸起的源极 - 漏极结构。

公开(公告)号：US20140353767A1

公开(公告)日：2014-12-04

申请号：US13906505

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Balasubramanian Pranatharthiharan

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。

公开(公告)号：US20140353760A1

公开(公告)日：2014-12-04

申请号：US13907613

申请日：2013-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract translation: 描述了用于在体基板上将诸如Si和SiGe的两种半导体材料类型的finFET共集成的方法。 用于finFET的鳍可以形成在第一半导体类型的外延层中，并被绝缘体覆盖。 可以去除一部分翅片以在绝缘体中形成空隙，并且可以通过在空隙中外延生长第二类型的半导体材料来填充空隙。 共同集成的finFET可以形成在相同的器件级。

公开(公告)号：US08860123B1

公开(公告)日：2014-10-14

申请号：US13852720

申请日：2013-03-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/792 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US11069682B2

公开(公告)日：2021-07-20

申请号：US16751036

申请日：2020-01-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/8234

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US10134895B2

公开(公告)日：2018-11-20

申请号：US13692632

申请日：2012-12-03

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.