公开(公告)号：US20230121780A1

公开(公告)日：2023-04-20

申请号：US18081884

申请日：2022-12-15

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/31

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20190067180A1

公开(公告)日：2019-02-28

申请号：US16110121

申请日：2018-08-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David AUCHERE ,  Laurent SCHWARZ ,  Deborah COGONI ,  Eric SAUGIER

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/16235 ,  H05K1/185 ,  H05K2201/10621 ,  H05K2201/10636

Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.

公开(公告)号：US20230015669A1

公开(公告)日：2023-01-19

申请号：US17945822

申请日：2022-09-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David AUCHERE ,  Claire LAPORTE ,  Deborah COGONI ,  Laurent SCHWARTZ

IPC: H01L23/50 ,  H01L23/31

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

公开(公告)号：US20190148334A1

公开(公告)日：2019-05-16

申请号：US16249122

申请日：2019-01-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/552

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20220301976A1

公开(公告)日：2022-09-22

申请号：US17698749

申请日：2022-03-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE

IPC: H01L23/42 ,  H01L23/00 ,  H01L21/52

Abstract: Electronic device comprising an electronic chip, a support substrate and a protection cover, the substrate and the cover being assembled so as to form a cavity housing the chip, at least one port equipped with a unidirectional valve being provided in the substrate or the cover, and making it possible to evacuate gas from the inside of the cavity to the outside of the cavity.

公开(公告)号：US20210104457A1

公开(公告)日：2021-04-08

申请号：US17064119

申请日：2020-10-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David AUCHERE ,  Claire LAPORTE ,  Deborah COGONI ,  Laurent SCHWARTZ

IPC: H01L23/50 ,  H01L23/31

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

公开(公告)号：US20240038607A1

公开(公告)日：2024-02-01

申请号：US18226409

申请日：2023-07-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fanny LAPORTE ,  David AUCHERE

IPC: H01L23/13 ,  H01L25/16 ,  H01L23/00 ,  H01L21/306

CPC classification number: H01L23/13 ,  H01L25/165 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L21/306 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15151 ,  H01L2924/16151 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/16235

Abstract: An integrated circuit package includes a cavity within which a circuit device is contained. At least one through hole is provided in at least one wall of the cavity. The at least one through hole includes at least one first portion flaring towards the cavity with a frustoconical shape, for example.

公开(公告)号：US20220028844A1

公开(公告)日：2022-01-27

申请号：US17374868

申请日：2021-07-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Deborah COGONI ,  David AUCHERE ,  Laurent SCHWARTZ ,  Claire Laporte

IPC: H01L25/16 ,  H01G4/38

Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.

公开(公告)号：US20250070081A1

公开(公告)日：2025-02-27

申请号：US18947819

申请日：2024-11-14

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/552

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20200305283A1

公开(公告)日：2020-09-24

申请号：US16815554

申请日：2020-03-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fabien QUERCIA ,  David AUCHERE ,  Norbert CHEVRIER ,  Fabien CORSAT

IPC: H05K1/18 ,  H05K3/34

Abstract: A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.