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公开(公告)号：US10381344B2
公开(公告)日：2019-08-13
申请号：US15897524
申请日：2018-02-15
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Olivier Weber , Emmanuel Richard , Philippe Boivin
IPC: H01L27/06 , H01L21/84 , H01L27/24 , H01L21/8249 , H01L29/732 , H01L45/00 , H01L29/417 , H01L29/66 , H01L27/12 , H01L29/08
Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
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公开(公告)号：US11818901B2
公开(公告)日：2023-11-14
申请号：US17489425
申请日：2021-09-29
Inventor： Philippe Boivin , Jean Jacques Fagot , Emmanuel Petitprez , Emeline Souchier , Olivier Weber
IPC: H01L21/8222 , H10B63/00 , H10N70/20 , H10N70/00
CPC classification number: H10B63/32 , H10N70/231 , H10N70/826
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
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公开(公告)号：US11653582B2
公开(公告)日：2023-05-16
申请号：US16184246
申请日：2018-11-08
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
CPC classification number: H10N70/8616 , G11C13/0004 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/882 , G11C2013/008
Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
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公开(公告)号：US10482957B2
公开(公告)日：2019-11-19
申请号：US15978003
申请日：2018-05-11
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe Boivin , Simon Jeannot , Olivier Weber
Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.
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公开(公告)号：US11152430B2
公开(公告)日：2021-10-19
申请号：US16375571
申请日：2019-04-04
Inventor： Philippe Boivin , Jean Jacques Fagot , Emmanuel Petitprez , Emeline Souchier , Olivier Weber
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
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Patent Agency Ranking
公开(公告)号：US10332808B2
公开(公告)日：2019-06-25
申请号：US15897003
申请日：2018-02-14
Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Julien , Stephan Niel , Emmanuel Richard , Olivier Weber
IPC: H01L21/00 , H01L21/84 , H01L29/51 , H01L21/8234 , H01L21/28 , H01L27/12 , H01L27/092
Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.
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公开(公告)号：US20180175022A1
公开(公告)日：2018-06-21
申请号：US15897524
申请日：2018-02-15
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Olivier Weber , Emmanuel Richard , Philippe Boivin
IPC: H01L27/06 , H01L27/24 , H01L21/84 , H01L29/732 , H01L45/00 , H01L21/8249
CPC classification number: H01L27/0623 , H01L21/8249 , H01L21/84 , H01L27/1207 , H01L27/2445 , H01L29/0813 , H01L29/41708 , H01L29/66303 , H01L29/732 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/126 , H01L45/16
Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
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公开(公告)号：US12232435B2
公开(公告)日：2025-02-18
申请号：US18130184
申请日：2023-04-03
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
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公开(公告)号：US20180269115A1
公开(公告)日：2018-09-20
申请号：US15897003
申请日：2018-02-14
Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Julien , Stephan Niel , Emmanuel Richard , Olivier Weber
CPC classification number: H01L21/84 , H01L21/28008 , H01L21/82345 , H01L21/823462 , H01L27/0922 , H01L27/1207 , H01L29/51
Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.
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公开(公告)号：US09929146B2
公开(公告)日：2018-03-27
申请号：US15454788
申请日：2017-03-09
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Olivier Weber , Emmanuel Richard , Philippe Boivin
IPC: H01L27/06 , H01L29/732 , H01L21/84 , H01L21/8249 , H01L45/00 , H01L27/24
CPC classification number: H01L27/0623 , H01L21/8249 , H01L21/84 , H01L27/1207 , H01L27/2445 , H01L29/0813 , H01L29/41708 , H01L29/66303 , H01L29/732 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/126 , H01L45/16
Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
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