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公开(公告)号：US20200264648A1
公开(公告)日：2020-08-20
申请号：US16867299
申请日：2020-05-05
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco IPPOLITO , Mario CHIRICOSTA
Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.
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公开(公告)号：US20180313699A1
公开(公告)日：2018-11-01
申请号：US15957999
申请日：2018-04-20
Applicant: STMicroelectronics S.r.l.
Inventor： Michele VAIANA , Paolo PESENTI , Mario CHIRICOSTA , Calogero Marco IPPOLITO , Mario MAIORE
CPC classification number: G01K3/14 , G01K7/02 , G01K7/021 , H03H17/02 , H03M3/43 , H03M3/456 , H03M3/458
Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
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公开(公告)号：US20160347606A1
公开(公告)日：2016-12-01
申请号：US14962945
申请日：2015-12-08
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Giuseppe BRUNO , Sebastiano CONTI , Mario CHIRICOSTA , Michele VAIANA , Calogero Marco IPPOLITO , Mario MAIORE , Daniele CASELLA
IPC: B81B7/00
CPC classification number: B81B7/007 , B81B7/02 , B81B2201/0264 , B81B2201/0292 , B81B2207/094 , G01L19/0092 , G01N27/223 , H01L23/3121 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
Abstract: A packaged sensor assembly includes: a packaging structure, having at least one opening; a humidity sensor and a pressure sensor, which are housed inside the packaging structure and communicate fluidically with the outside through the opening, and a control circuit, operatively coupled to the humidity sensor and to the pressure sensor; wherein the humidity sensor and the control circuit are integrated in a first chip, and the pressure sensor is integrated in a second chip distinct from the first chip and bonded to the first chip.
Abstract translation: 包装传感器组件包括：具有至少一个开口的包装结构; 湿度传感器和压力传感器，其容纳在包装结构内并通过开口与外部流体连通;以及控制电路，可操作地耦合到湿度传感器和压力传感器; 其中所述湿度传感器和所述控制电路集成在第一芯片中，并且所述压力传感器集成在与所述第一芯片不同的第二芯片中并且被结合到所述第一芯片。
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Patent Agency Ranking
4.发明申请公开(公告)号：US20200259474A1
公开(公告)日：2020-08-13
申请号：US16781493
申请日：2020-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco IPPOLITO , Michele VAIANA , Angelo RECCHIA
Abstract: An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.
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5.发明申请公开(公告)号：US20200256898A1
公开(公告)日：2020-08-13
申请号：US16781598
申请日：2020-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Michele VAIANA , Calogero Marco IPPOLITO , Angelo RECCHIA , Antonio CICERO , Pierpaolo LOMBARDO
Abstract: An amplification interface includes an input terminal receiving a sensor current and an output terminal supplying an output voltage. An analog integrator is connected to the input terminal and supplies the output voltage. A current generator is connected to the input of the analog integrator and generates a compensation current based on a drive signal. A control circuit generates the drive signal for the current generator based on a control signal representing an offset in the sensor current supplied by the sensor. The current generator generates, based on the driving signal, a positive or negative current. The control circuit determines a first duration and a second duration as a function of the control signal representing the offset in the sensor current, during the measurement interval, and sets the driving signal to a first logic value for the first duration and to a second logic value for the second duration.
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公开(公告)号：US20240106451A1
公开(公告)日：2024-03-28
申请号：US18370052
申请日：2023-09-19
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco IPPOLITO , Michele VAIANA
CPC classification number: H03M1/1255 , H03M1/1215 , H03M3/454 , H03M3/462
Abstract: A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.
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公开(公告)号：US20220302890A1
公开(公告)日：2022-09-22
申请号：US17687079
申请日：2022-03-04
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco IPPOLITO , Michele VAIANA
IPC: H03F3/45
Abstract: An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.
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公开(公告)号：US20220163572A1
公开(公告)日：2022-05-26
申请号：US17670858
申请日：2022-02-14
Applicant: STMicroelectronics S.r.l.
Inventor： Michele VAIANA , Calogero Marco IPPOLITO , Angelo RECCHIA , Antonio CICERO , Pierpaolo LOMBARDO
Abstract: An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.
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