公开(公告)号：US12142536B2

公开(公告)日：2024-11-12

申请号：US18082155

申请日：2022-12-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L21/66 ,  H01L23/00 ,  H01L29/00 ,  H03K19/00

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

公开(公告)号：US11637106B2

公开(公告)日：2023-04-25

申请号：US17493226

申请日：2021-10-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L29/66 ,  H01L27/108 ,  H01L27/11521 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

公开(公告)号：US20220328509A1

公开(公告)日：2022-10-13

申请号：US17700323

申请日：2022-03-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H01L27/11524 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/788 ,  H01L29/66

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

公开(公告)号：US20220199632A1

公开(公告)日：2022-06-23

申请号：US17540029

申请日：2021-12-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H01L27/112

Abstract: The present description concerns a ROM including at least one first rewritable memory cell.

公开(公告)号：US11139303B2

公开(公告)日：2021-10-05

申请号：US17026869

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US10535672B2

公开(公告)日：2020-01-14

申请号：US15486434

申请日：2017-04-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L27/11524 ,  H01L29/06 ,  H01L27/06

Abstract: A well of a first conductivity type is insulated from a substrate of the same first conductivity type by a structure of a triple well type. The structure includes a trench having an electrically conductive central part enclosed in an insulating sheath. The trench supports a first electrode of a decoupling capacitor, with a second electrode provided by the well.

公开(公告)号：US20190341390A1

公开(公告)日：2019-11-07

申请号：US16391768

申请日：2019-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H01L27/1157 ,  H01L27/11565 ,  G11C5/06

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US20180247874A1

公开(公告)日：2018-08-30

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01C7/12 ,  H01L27/08 ,  H01L49/02 ,  H01L21/74

CPC classification number: H01L21/823493 ,  H01C7/126 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/765 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/8605

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US12289884B2

公开(公告)日：2025-04-29

申请号：US17747540

申请日：2022-05-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Romeric Gay ,  Abderrezak Marzaki

IPC: H10B41/40 ,  H10B41/30

Abstract: A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.

公开(公告)号：US20240324196A1

公开(公告)日：2024-09-26

申请号：US18735967

申请日：2024-06-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10

CPC classification number: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/66825 ,  H01L29/7884 ,  H01L29/40114 ,  H01L29/7883 ,  H10B41/10

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.