公开(公告)号：US09831357B2

公开(公告)日：2017-11-28

申请号：US13907280

申请日：2013-05-31

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics R&D Limited

Inventor： Yonggang Jin ,  David Lawson ,  Colin Campbell ,  Anandan Ramasamy

IPC: H01L31/0216 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0232 ,  H01L31/101

CPC classification number: H01L31/02165 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02162 ,  H01L31/02164 ,  H01L31/02327 ,  H01L31/1013 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Embodiments of the present disclosure are directed to optical packages having a package body that includes a light protection coating on at least one surface of a transparent material. The light protection coating includes one or more openings to allow light to be transmitted to the optical device within the package body. In one embodiment, the light protection coating and the openings allow substantially perpendicular radiation to be directed to the optical device within the package body. In one exemplary embodiment the light protection coating is located on an outer surface of the transparent material. In another embodiment, the light protection coating is located on an inner surface of the transparent material inside of the package body.

公开(公告)号：US10115842B2

公开(公告)日：2018-10-30

申请号：US15802271

申请日：2017-11-02

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics R&D Limited

Inventor： Yonggang Jin ,  David Lawson ,  Colin Campbell ,  Anandan Ramasamy

IPC: H01L31/0216 ,  H01L31/0232 ,  H01L31/0203 ,  H01L31/02 ,  H01L31/101

Abstract: Embodiments of the present disclosure are directed to optical packages having a package body that includes a light protection coating on at least one surface of a transparent material. The light protection coating includes one or more openings to allow light to be transmitted to the optical device within the package body. In one embodiment, the light protection coating and the openings allow substantially perpendicular radiation to be directed to the optical device within the package body. In one exemplary embodiment the light protection coating is located on an outer surface of the transparent material. In another embodiment, the light protection coating is located on an inner surface of the transparent material inside of the package body.

公开(公告)号：US20140353788A1

公开(公告)日：2014-12-04

申请号：US13907280

申请日：2013-05-31

Applicant: STMicroelectronics R&D Limited ,  STMicroelectronics Pte Ltd.

Inventor： Yonggang Jin ,  David Lawson ,  Colin Campbell ,  Anandan Ramasamy

IPC: H01L31/0216

CPC classification number: H01L31/02165 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02162 ,  H01L31/02164 ,  H01L31/02327 ,  H01L31/1013 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Embodiments of the present disclosure are directed to optical packages having a package body that includes a light protection coating on at least one surface of a transparent material. The light protection coating includes one or more openings to allow light to be transmitted to the optical device within the package body. In one embodiment, the light protection coating and the openings allow substantially perpendicular radiation to be directed to the optical device within the package body. In one exemplary embodiment the light protection coating is located on an outer surface of the transparent material. In another embodiment, the light protection coating is located on an inner surface of the transparent material inside of the package body.

Abstract translation: 本公开的实施例涉及具有封装主体的光学封装，该封装主体在透明材料的至少一个表面上包括防光涂层。 防光涂层包括一个或多个开口，以允许光被传输到封装主体内的光学装置。 在一个实施例中，光保护涂层和开口允许基本上垂直的辐射被引导到封装主体内的光学装置。 在一个示例性实施例中，防光涂层位于透明材料的外表面上。 在另一个实施例中，防光涂层位于包装体内部的透明材料的内表面上。

公开(公告)号：US11231386B2

公开(公告)日：2022-01-25

申请号：US15812731

申请日：2017-11-14

Applicant: STMicroelectronics Pte Ltd

Inventor： Jerome Teysseyre ,  Yonggang Jin ,  Suman Cherian

IPC: G01N27/406 ,  G01N27/407 ,  H05K1/18

Abstract: A compact microelectronic gas sensor module includes electrical contacts formed in such a way that they do not consume real estate on an integrated circuit chip. Using such a design, the package can be miniaturized further. The gas sensor is packaged together with a custom-designed Application Specific Integrated Circuit (ASIC) that provides circuitry for processing sensor signals to identify gas species within a sample under test. In one example, the output signal strength of the sensor is enhanced by providing an additional metal surface area in the form of pillars exposed to an electrolytic gas sensing compound, while reducing the overall package size. In some examples, bottom side contacts are formed on the underside of the substrate on which the gas sensor is formed. Sensor electrodes may be electrically coupled to the ASIC directly, or indirectly by vias.

公开(公告)号：US10381504B2

公开(公告)日：2019-08-13

申请号：US15969908

申请日：2018-05-03

Applicant: STMicroelectronics Pte Ltd

Inventor： Yonggang Jin ,  Wee Chin Judy Lim

IPC: H01L31/16 ,  H01L31/0232 ,  H01L31/18 ,  H03K17/94 ,  H03K17/96 ,  H01L31/167 ,  G01S17/02 ,  G01S7/481 ,  H01L25/16 ,  G01V8/12 ,  H01L21/56

Abstract: An optical detection sensor functions as a proximity detection sensor that includes an optical system and a selectively transmissive structure. Electromagnetic radiation such as laser light can be emitted through a transmissive portion of the selectively transmissive structure. A reflected beam can be detected to determine the presence of an object. The sensor is formed by encapsulating the transmissive structure in a first encapsulant body and encapsulating the optical system in a second encapsulant body. The first and second encapsulant bodies are then joined together. In a wafer scale assembling the structure resulting from the joined encapsulant bodies is diced to form optical detection sensors.

公开(公告)号：US20140175649A1

公开(公告)日：2014-06-26

申请号：US13727206

申请日：2012-12-26

Applicant: STMICROELECTRONICS PTE. LTD

Inventor： Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.

Abstract translation: 电子器件可以包括其中具有第一导电通孔的底部互连层。 电子设备还可以包括由所述底部互连层承载的集成电路（IC）和在底部互连层上并围绕IC的封装材料。 封装层可以具有与第一导电通孔对准的第二导电通孔。 第二导电通孔的横截面积可以大于第一导电通孔的横截面面积。

公开(公告)号：US20160035590A1

公开(公告)日：2016-02-04

申请号：US14450554

申请日：2014-08-04

Applicant: STMicroelectronics Pte Ltd

Inventor： Yonggang Jin

IPC: H01L21/56 ,  H01L25/07 ,  H01L21/78 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L21/563 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer.

Abstract translation: 一个或多个实施例涉及包括多个半导体芯片的系统级封装（SiP）和在封装层中一起模塑的插入器。 也就是说，可以使用单个处理步骤来将半导体芯片和插入器封装在封装层中。 此外，在固化或固化之前，封装层能够在半导体芯片和插入件之间流动，以为半导体芯片提供进一步的机械支撑。 因此，形成SiP的工艺减少，加工时间更短，成本更低。 另外，本文所述的一个或多个实施例减少或消除插入件的翘曲。

公开(公告)号：US09252030B1

公开(公告)日：2016-02-02

申请号：US14450554

申请日：2014-08-04

Applicant: STMicroelectronics Pte Ltd

Inventor： Yonggang Jin

IPC: H01L23/49 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/498 ,  H01L25/07

CPC classification number: H01L21/563 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer.

Abstract translation: 一个或多个实施例涉及包括多个半导体芯片的系统级封装（SiP）和在封装层中一起模塑的插入器。 也就是说，可以使用单个处理步骤来将半导体芯片和插入器封装在封装层中。 此外，在固化或固化之前，封装层能够在半导体芯片和插入件之间流动，以为半导体芯片提供进一步的机械支撑。 因此，形成SiP的工艺减少，加工时间更短，成本更低。 此外，本文所述的一个或多个实施例减少或消除插入件的翘曲。

公开(公告)号：US08860228B2

公开(公告)日：2014-10-14

申请号：US13727206

申请日：2012-12-26

Applicant: STMicroelectronics Pte. Ltd

Inventor： Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.

Abstract translation: 电子器件可以包括其中具有第一导电通孔的底部互连层。 电子设备还可以包括由所述底部互连层承载的集成电路（IC）和在底部互连层上并围绕IC的封装材料。 封装层可以具有与第一导电通孔对准的第二导电通孔。 第二导电通孔的横截面积可以大于第一导电通孔的横截面面积。

公开(公告)号：US20140103521A1

公开(公告)日：2014-04-17

申请号：US13652937

申请日：2012-10-16

Applicant: STMICROELECTRONICS PTE. LTD

Inventor： Yonggang Jin ,  How Yuan HWANG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.

Abstract translation: 电子设备可以包括底部互连层和由底部互连层承载的集成电路（IC）。 电子设备还可以包括底部互连层上的封装材料并横向包围IC。 电子器件还可以包括穿过封装材料的底部互连层上的导电柱。 至少一个导电柱和封装材料的相邻部分可以相对于IC和封装材料的相邻部分具有减小的高度，并且可以限定至少一个接触凹部。 所述至少一个接触凹部可以与所述封装材料的周边向内间隔开。