公开(公告)号：US20230246088A1

公开(公告)日：2023-08-03

申请号：US18156976

申请日：2023-01-19

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Giuseppe Greco ,  Paolo BADALA' ,  Fabrizio ROCCAFORTE ,  Monia SPERA

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/7786

Abstract: A process for manufacturing a HEMT device includes forming a conductive region on a work body having a semiconductive heterostructure. To obtain the conductive region, a first reaction region having carbon is formed on the heterostructure and a metal stack is formed having a second reaction region in contact with the first reaction region. The work body is annealed, so that the first reaction region reacts with the second reaction region, thus forming an interface portion of the conductive region. The interface portion is of a compound having carbon and is in ohmic contact with the semiconductive hetero structure.

公开(公告)号：US20230246086A1

公开(公告)日：2023-08-03

申请号：US18156120

申请日：2023-01-18

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Raffaella LO NIGRO ,  Emanuela SCHILIRÒ ,  Fabrizio ROCCAFORTE

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28185 ,  H01L29/205 ,  H01L29/401 ,  H01L29/517 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/66462

Abstract: The present disclosure is directed to a wide band gap transistor that includes a semiconductor structure, having at least one wide band gap semiconductor layer of gallium nitride or silicon carbide, an insulating gate structure and a gate electrode, separated from the semiconductor structure by the insulating gate structure. The insulating gate structure contains a mixture of aluminum, hafnium and oxygen.

公开(公告)号：US20220208977A1

公开(公告)日：2022-06-30

申请号：US17698986

申请日：2022-03-18

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Mario Giuseppe SAGGIO

IPC: H01L29/423 ,  H01L27/06 ,  H01L29/16 ,  H01L29/872

Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.

公开(公告)号：US20200152779A1

公开(公告)日：2020-05-14

申请号：US16738935

申请日：2020-01-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US20240079455A1

公开(公告)日：2024-03-07

申请号：US18364180

申请日：2023-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Edoardo ZANETTI ,  Mario Giuseppe SAGGIO

IPC: H01L29/16 ,  H01L29/51 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L29/1608 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/872

Abstract: Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.

公开(公告)号：US20230299148A1

公开(公告)日：2023-09-21

申请号：US18183866

申请日：2023-03-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Fabrizio ROCCAFORTE ,  Gabriele BELLOCCHI ,  Marilena VIVONA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H01L29/45

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/872 ,  H01L29/66143 ,  H01L29/45

Abstract: A method for manufacturing an electronic device includes forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

公开(公告)号：US20230246100A1

公开(公告)日：2023-08-03

申请号：US18158986

申请日：2023-01-24

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Filippo GIANNAZZO ,  Giuseppe Greco ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/285 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3205

CPC classification number: H01L29/7786 ,  H01L29/66431 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42316 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/0272 ,  H01L21/28506 ,  H01L21/3086 ,  H01L21/3081 ,  H01L21/3065 ,  H01L21/32051

Abstract: An enhancement mode high electron-mobility transistor (HEMT) device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas, 2DEG. The HEMT device includes a gate structure which extends on the top surface of the semiconductor body, is biasable to electrically control the 2DEG and includes a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is of conductive material and the functional layer is of two-dimensional semiconductor material and includes a first doped portion with P-type electrical conductivity, which extends on the top surface of the semiconductor body and is interposed between the semiconductor body and the gate contact along a first axis.

公开(公告)号：US20230261100A1

公开(公告)日：2023-08-17

申请号：US18167623

申请日：2023-02-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Andrea SEVERINO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/1608 ,  H01L29/66462

Abstract: A manufacturing process forms an HEMT device. For the manufacturing process includes forming, from a wafer of silicon carbide having a surface, an epitaxial layer of silicon carbide on the surface of the wafer A semiconductive heterostructure is formed on the epitaxial layer, and the wafer of silicon carbide is removed.

公开(公告)号：US20230087112A1

公开(公告)日：2023-03-23

申请号：US17939842

申请日：2022-09-07

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Filippo GIANNAZZO ,  Giuseppe Greco ,  Fabrizio ROCCAFORTE ,  Simone RASCUNA'

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/45 ,  H01L29/868 ,  H01L29/872 ,  H01L21/04

Abstract: Merged-PiN-Schottky, MPS, device comprising: a solid body having a first electrical conductivity; an implanted region extending into the solid body facing a front side of the solid body, having a second electrical conductivity opposite to the first electrical conductivity; and a semiconductor layer extending on the front side, of a material which is a transition metal dichalcogenide, TMD. A first region of the semiconductor layer has the second electrical conductivity and extends in electrical contact with the implanted region, and a second region of the semiconductor layer has the first electrical conductivity and extends adjacent to the first region and in electrical contact with a respective surface portion of the front side having the first electrical conductivity.

公开(公告)号：US20220208961A1

公开(公告)日：2022-06-30

申请号：US17559859

申请日：2021-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patrick FIORENZA ,  Fabrizio ROCCAFORTE ,  Edoardo ZANETTI ,  Mario Giuseppe SAGGIO

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/66

Abstract: A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.