公开(公告)号：US20040170057A1

公开(公告)日：2004-09-02

申请号：US10748696

申请日：2003-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Osama Khouri ,  Roberto Ravasio ,  Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C29/76

Abstract: The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

Abstract translation: 该设备包括用于扇区重新映射的电路，其具有与多路复用器单元相关联并且与多路复用器单元进行数据通信的CAM（内容可寻址存储器）单元。 CAM单元检测到扇区有故障，它提供替换扇区的预编程地址，并激活执行替换的多路复用器。 因此，有缺陷的扇区和地址图的相应位置有利地位于寻址区的后方。 因此，寻址区域是连续的，从而可以容易地存储和检索信息。

公开(公告)号：US20030133325A1

公开(公告)日：2003-07-17

申请号：US10340207

申请日：2003-01-10

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Silvagni ,  Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C16/08 ,  G11C2216/22

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract translation: 存储器件包括组织成多个扇区的存储器单元的阵列，并且本地字线和本地位线连接到每个相应扇区中的存储器单元。 主读取字线和主程序字线连接到每个扇区中的本地字线。 主读取行解码器连接到主读取字线，连接到主程序字线的主程序行解码器。 主读位线和主程序位线连接到每个扇区中的本地位线。 主读取列解码器连接到主读取位线，主程序列解码器连接到主程序字线。 读地址总线连接到主读行解码器和主读列解码器，以提供地址。 程序地址总线连接到主读取列解码器和主程序行解码器，以向其提供地址。

公开(公告)号：US20020181277A1

公开(公告)日：2002-12-05

申请号：US10123874

申请日：2002-04-16

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C7/062 ,  G11C7/04 ,  G11C7/22 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/063 ,  G11C2211/5634

Abstract: The method for timing reading of a memory cell envisages supplying the memory cell (with a constant current by means of a first capacitive element, integrating said current in a time interval, and controlling the duration of the time interval in such a way as to compensate for any deviations in the current from a nominal value. In particular, a reference current is supplied to a reference cell by means of a second capacitive element; next, a first voltage present on the second capacitive element is measured; finally, the memory cell is deactivated when the first voltage is equal to a second voltage, which is constant.

Abstract translation: 用于定时读取存储器单元的方法设想为存储器单元提供（通过第一电容元件的恒定电流，在时间间隔内积分所述电流，并以这样的方式来控制时间间隔的持续时间，以便补偿 特别是通过第二电容元件将参考电流提供给参考电池;接下来，测量存在于第二电容元件上的第一电压;最后，存储单元 当第一电压等于第二电压时，其被停用，该第二电压是恒定的。

公开(公告)号：US20020054505A1

公开(公告)日：2002-05-09

申请号：US09976473

申请日：2001-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C11/5642 ,  G11C8/00 ,  G11C11/56 ,  G11C11/5621

Abstract: The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

Abstract translation: 数据管理方法适用于具有由多个存储单元形成的存储器阵列的多级非易失性存储器件。 每个存储器单元存储不是2的整数倍的位数，例如3。 以这种方式，一个数据字节存储在非整数个存储单元中。 管理方法包括通过对预设数量的相邻存储器单元进行编程，以相同的时钟周期存储由多个字节形成的数据字。 通过在相同的时钟周期中读取存储的数据字来执行读取。

公开(公告)号：US20020041534A1

公开(公告)日：2002-04-11

申请号：US09919789

申请日：2001-07-31

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Gastaldi ,  Paolo Cappelletti ,  Giulio Casagrande ,  Giovanni Campardo ,  Rino Micheloni

IPC: G11C008/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

Abstract translation: 诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。 属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列 形成包。 具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。 因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

公开(公告)号：US20010030554A1

公开(公告)日：2001-10-18

申请号：US09782173

申请日：2001-02-12

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Ghezzi ,  Donato Ferrario ,  Emilio Yero ,  Giovanni Campardo

IPC: H03K019/177

CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Abstract translation: 可编程逻辑阵列（PLA）包括至少一个AND平面，其包括以行和列排列的晶体管阵列。 属于同一列的晶体管可以彼此串联连接。 串联连接的晶体管的两个端部导电端子可以分别耦合到电源电压轨和参考。 阵列的第一行和最后一行的晶体管可以使它们的控制端耦合到各自相对的使能/禁止电位。 除了第一行和最后一行，第一，第二和第三控制行都与数组的每一行相关联。 除了第一行和最后一行之外，每行的每个晶体管可以将其控制端连接到与其行相关联的三条控制线之一。 PLA可以替代地包括至少一个OR平面。

公开(公告)号：US20040223399A1

公开(公告)日：2004-11-11

申请号：US10675805

申请日：2003-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Rino Micheloni

IPC: G11C008/02

CPC classification number: G11C29/82 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008 ,  G11C29/83 ,  G11C29/832

Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.

Abstract translation: 本发明涉及一种用于精确定位擦除故障存储器单元的方法和可编程和电可擦除类型的相关集成非易失性存储器件，其包括以行和列布置的存储器单元的分区阵列，具有至少一个行 - 每个扇区的解码电路部分被提供正和负电压。 该方法在负擦除算法问题上变得可操作，并且包括以下步骤：强制尚未被完全擦除的扇区的读取条件; 扫描所述扇区的行以检查是否存在指示故障状态的杂散电流; 发现故障行并将其电隔离以将其重新寻址到在同一扇区中提供的冗余行。

公开(公告)号：US20020192892A1

公开(公告)日：2002-12-19

申请号：US10133231

申请日：2002-04-26

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: H01L021/8238

CPC classification number: G11C11/5621 ,  G11C5/147 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5634

Abstract: The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second reference circuit respectively connected to said first and said second memory cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage; and a voltage divider having a first connection node and a second connection node respectively connected to the output terminals of the first reference circuit and of the second reference circuit to receive, respectively, the first reference voltage and the second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.

Abstract translation: 用于产生用于读取多电平存储器单元的参考电压的电路包括：分别具有第一参考编程电平和第二参考编程电平的第一存储单元和第二存储单元; 分别连接到所述第一和所述第二存储单元的第一参考电路和第二参考电路，并具有分别提供第一参考电压和第二参考电压的相应输出端; 以及分压器，具有分别连接到第一参考电路和第二参考电路的输出端的第一连接节点和第二连接节点，以分别接收第一参考电压和第二参考电压，以及多个 中间节点以相等的距离提供相应的第三参考电压。

公开(公告)号：US20020149965A1

公开(公告)日：2002-10-17

申请号：US10076023

申请日：2002-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Rino Micheloni

IPC: G11C016/26

CPC classification number: G11C11/56 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26

Abstract: The method for reading a memory cell includes supplying the cell with a first charge quantity through a capacitive integration element and reintegrating the first charge quantity through a plurality of second charge quantities supplied alternately and in succession to the capacitive integration element. In a first embodiment, the second charge quantities are initially stored in a plurality of capacitive charge-regeneration elements connected alternately and in succession to the capacitive integration element; the second charge quantities are then shared between the capacitive integration element and the capacitive charge-regeneration elements.

Abstract translation: 用于读取存储器单元的方法包括通过电容积分元件向单元提供第一电荷量，并通过交替地并依次提供给电容积分元件的多个第二电荷量重新整合第一电荷量。 在第一实施例中，第二电荷量最初被存储在多个电容性电荷再生元件中，这些元件是电容积分元件交替连续地连接的; 然后在电容积分元件和电容充电再生元件之间共享第二电荷量。

公开(公告)号：US20020149964A1

公开(公告)日：2002-10-17

申请号：US10047918

申请日：2002-01-14

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Rino Micheloni

IPC: G11C011/34

CPC classification number: G11C11/5621 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26

Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In a first operating mode, initially a first capacitor and a second capacitor are respectively charged to a first charge value and to a second charge value. The second capacitor is discharged through the memory cell at a constant current in a preset time; the first charge is shared between the first capacitor and the second capacitor; and then the shared charge is measured.

Abstract translation: 用于读取存储器单元的方法是基于通过电容元件提供给存储单元的电流的时间积分。 电容元件最初被充电，然后在预设时间内线性地放电，同时存储单元被偏置在恒定电压。 在第一操作模式中，最初将第一电容器和第二电容器分别充电到第一充电值和第二充电值。 第二电容器在预定时间内以恒定电流通过存储单元放电; 第一电荷在第一电容器和第二电容器之间共享; 然后测量共享费用。