公开(公告)号：US09978780B2

公开(公告)日：2018-05-22

申请号：US15095646

申请日：2016-04-11

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young-Wook Lee ,  Jang-Soo Kim

IPC: G02F1/1343 ,  H01L27/12 ,  G02F1/1365 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1365 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2001/13629 ,  H01L27/1248

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

公开(公告)号：US09520412B2

公开(公告)日：2016-12-13

申请号：US14798123

申请日：2015-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L21/4757 ,  H01L21/441 ,  H01L21/475 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

公开(公告)号：US08975145B2

公开(公告)日：2015-03-10

申请号：US14168971

申请日：2014-01-30

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

IPC: H01L33/44 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

公开(公告)号：US11075223B2

公开(公告)日：2021-07-27

申请号：US16571676

申请日：2019-09-16

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun Lee ,  Katsumi Abe ,  Young-Wook Lee

IPC: H01L27/12 ,  H01L29/24 ,  H01L23/528 ,  H01L23/31 ,  H01L29/66 ,  H01L29/786 ,  H01L21/56 ,  H01L21/768 ,  G09G3/3266 ,  H01L33/00 ,  H01L33/42 ,  G09G3/36

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

公开(公告)号：US10418387B2

公开(公告)日：2019-09-17

申请号：US15416373

申请日：2017-01-26

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun Lee ,  Katsumi Abe ,  Young-Wook Lee

IPC: G09G3/3266 ,  G09G3/36 ,  H01L27/12 ,  H01L29/24 ,  H01L23/528 ,  H01L23/31 ,  H01L29/66 ,  H01L29/786 ,  H01L21/56 ,  H01L21/768

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

公开(公告)号：US20170141128A1

公开(公告)日：2017-05-18

申请号：US15416373

申请日：2017-01-26

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun LEE ,  Katsumi Abe ,  Young-Wook Lee

IPC: H01L27/12 ,  G09G3/36 ,  H01L29/786

CPC classification number: H01L27/124 ,  G09G3/3266 ,  G09G3/3677 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/3171 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

公开(公告)号：US09443877B2

公开(公告)日：2016-09-13

申请号：US14799060

申请日：2015-07-14

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC: H01L29/04 ,  H01L31/036 ,  H01L27/12 ,  H01L21/4757 ,  H01L21/441 ,  H01L21/475 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

公开(公告)号：US20200013805A1

公开(公告)日：2020-01-09

申请号：US16571676

申请日：2019-09-16

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun Lee ,  Katsumi Abe ,  Young-Wook Lee

IPC: H01L27/12 ,  H01L29/24 ,  H01L23/528 ,  H01L23/31 ,  H01L29/66 ,  H01L29/786 ,  H01L21/56 ,  H01L21/768 ,  G09G3/3266 ,  G09G3/36

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

公开(公告)号：US10355025B2

公开(公告)日：2019-07-16

申请号：US15813758

申请日：2017-11-15

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including gate wirings including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate wirings and the oxide semiconductor layer pattern, data wirings including a data line crossing the gate line, a source electrode connected to one side of the oxide semiconductor layer pattern, and a drain electrode connected to another side of the oxide semiconductor layer, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US09520419B2

公开(公告)日：2016-12-13

申请号：US14793183

申请日：2015-07-07

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A method of manufacturing a thin film transistor (TFT) array substrate includes forming a gate line and a gate electrode on a substrate, forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode, forming etch stop patterns at a thin-film transistor area and an area where the gate line and the data line overlap each other, forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode, and forming a data line extending in a direction intersecting the gate line.

Abstract translation: 制造薄膜晶体管（TFT）阵列基板的方法包括在基板上形成栅极线和栅电极，在栅极线和栅电极上形成栅极绝缘层和氧化物半导体层，形成蚀刻停止图案 在薄膜晶体管区域和栅极线和数据线彼此重叠的区域中，在氧化物半导体层和蚀刻停止图案上形成数据导体，数据导体包括源电极和漏极，构成 TFT与栅极电极一起形成，并且在与栅极线相交的方向上形成数据线。