公开(公告)号：US11812609B2

公开(公告)日：2023-11-07

申请号：US17218267

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Il Lee ,  Yu Jin Seo ,  Jun Eon Jin

IPC: H10B43/10 ,  H01L23/522 ,  H10B41/10 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

公开(公告)号：US11778821B2

公开(公告)日：2023-10-03

申请号：US17037074

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11575 ,  H10B43/27 ,  G11C8/14 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

公开(公告)号：US10825832B2

公开(公告)日：2020-11-03

申请号：US16780999

申请日：2020-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Mo Gu ,  Kyeong Jin Park ,  Hyun Mog Park ,  Byoung Il Lee ,  Tak Lee ,  Jun Ho Cha

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/1157

Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

公开(公告)号：US10566346B2

公开(公告)日：2020-02-18

申请号：US16108834

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tak Lee ,  Su Bin Kang ,  Ji Mo Gu ,  Yu Jin Seo ,  Byoung Il Lee ,  Jun Ho Cha

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11568 ,  H01L29/10 ,  H01L29/423 ,  H01L21/285 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

公开(公告)号：US10553605B2

公开(公告)日：2020-02-04

申请号：US15933695

申请日：2018-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Mo Gu ,  Kyeong Jin Park ,  Hyun Mog Park ,  Byoung Il Lee ,  Tak Lee ,  Jun Ho Cha

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

公开(公告)号：US10515819B2

公开(公告)日：2019-12-24

申请号：US15844681

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hoon Park ,  Joong Shik Shin ,  Byoung Il Lee ,  Jong Ho Woo ,  Eun Taek Jung ,  Jun Ho Cha

IPC: H01L27/11531 ,  H01L21/3105 ,  H01L21/763 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/11573 ,  H01L27/11592 ,  H01L21/762 ,  H01L21/311

Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.

公开(公告)号：US20190355736A1

公开(公告)日：2019-11-21

申请号：US16227822

申请日：2018-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SU BIN KANG ,  Byoung Il Lee ,  Ji Mo Gu ,  Yu Jin Seo ,  Tak Lee

IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

公开(公告)号：US20240397719A1

公开(公告)日：2024-11-28

申请号：US18791831

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

公开(公告)号：US12058863B2

公开(公告)日：2024-08-06

申请号：US18158605

申请日：2023-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H01L27/11582 ,  G11C7/18 ,  G11C8/14 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

公开(公告)号：US10515974B2

公开(公告)日：2019-12-24

申请号：US15925365

申请日：2018-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Il Lee ,  Ji Mo Gu ,  Tak Lee ,  Jun Ho Cha

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction.