公开(公告)号：US20220302017A1

公开(公告)日：2022-09-22

申请号：US17830811

申请日：2022-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Seung SONG ,  Kwang-Young LEE ,  Jonghyun LEE

IPC: H01L23/528 ,  H01L27/11 ,  H01L21/768

Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

公开(公告)号：US20220336661A1

公开(公告)日：2022-10-20

申请号：US17857608

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Hyun-Seung SONG ,  Hyo-Jin KIM ,  Kyoung-Mi PARK ,  Hwi-Chan JUN ,  SeungSeok HA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

公开(公告)号：US20150287829A1

公开(公告)日：2015-10-08

申请号：US14742710

申请日：2015-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGUN KIM ,  Dong-Hyun KIM ,  Hyun-Seung SONG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7853 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin portion protruding from a substrate. The fin portion includes a base part, an intermediate part on the base part, and a channel part on the intermediate part. A width of the intermediate part is less than a width of the base part and greater than a width of the channel part. A gate electrode coves both sidewalls and a top surface of the channel part, and a device isolation pattern covers both sidewalls of the base part and both sidewalls of the intermediate part.

公开(公告)号：US20210272893A1

公开(公告)日：2021-09-02

申请号：US17016977

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Seung SONG ,  Kwang-Young LEE ,  Jonghyun LEE

IPC: H01L23/528 ,  H01L27/11 ,  H01L21/768

Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

公开(公告)号：US20140203377A1

公开(公告)日：2014-07-24

申请号：US14161867

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung SONG ,  Kyung-Eun KIM ,  Jae-Kyun PARK

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/1104 ,  H01L2027/11812 ,  H01L2027/11838

Abstract: Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction. The third gate pattern has an asymmetric shape to the first gate pattern with respect to the first direction, and the fourth gate pattern is parallel to the third gate pattern in the first direction, and has an asymmetric shape to the second gate pattern with respect to the first direction. MOS transistors having good properties may be provided in a narrow horizontal area. The MOS transistors may be used in highly stacked semiconductor devices.

Abstract translation: 半导体器件包括设置在第一有源区上的第一栅极图案，第一有源区上的第二栅极图案，第二有源区上的第三栅极图案，以及第二有源区上的第四栅极图案。 第二栅极图案在第一方向上平行于第一栅极图案。 第三栅极图案相对于第一方向具有与第一栅极图案不对称的形状，并且第四栅极图案在第一方向上平行于第三栅极图案，并且相对于第二栅极图案具有与第二栅极图案不对称的形状 第一个方向。 可以在窄的水平区域中提供具有良好性能的MOS晶体管。 MOS晶体管可以用于高度堆叠的半导体器件中。

公开(公告)号：US20200027870A1

公开(公告)日：2020-01-23

申请号：US16395691

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Seok HA ,  Kyoung-Mi PARK ,  Hyun-Seung SONG ,  Keon Yong CHEON ,  Dae Won HA

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.

公开(公告)号：US20160020303A1

公开(公告)日：2016-01-21

申请号：US14670324

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi-Chan JUN ,  Deok-Han BAE ,  Hyun-Seung SONG ,  Seung-Seok HA

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656

Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

Abstract translation: 本公开的实施例涉及一种用于制造包括具有改善的电特性的场效应晶体管的半导体器件的方法。 根据本公开的实施例，可以使用设置在栅极部分上的金属硬掩模部分来有效地形成自对准接触插塞。 此外，通过使用金属硬掩模部分，可以提高用于形成自对准接触插塞的光刻胶掩模的工艺余量。

公开(公告)号：US20160005659A1

公开(公告)日：2016-01-07

申请号：US14692972

申请日：2015-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Seung SONG

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425

Abstract: Embodiments provide methods of manufacturing a semiconductor device. The method includes forming an interlayer insulating layer on a substrate; forming a plurality of contact holes penetrating the interlayer insulating layer, the plurality of contact holes arranged along a first direction and a second direction perpendicular to the first direction; and forming contacts in the contact holes, each contact hole being formed using a photo mask that is distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the first direction and distinct from a photo mask used for forming a contact hole immediately adjacent to each contact hole in the second direction, and top surfaces of the contacts being at a same level from the substrate.

Abstract translation: 实施例提供了制造半导体器件的方法。 该方法包括在衬底上形成层间绝缘层; 形成穿过所述层间绝缘层的多个接触孔，所述多个接触孔沿着与第一方向垂直的第一方向和第二方向布置; 并且在接触孔中形成触点，每个接触孔使用与用于在第一方向上形成与每个接触孔紧邻的接触孔的光掩模不同的光掩模形成，并且与用于形成 在第二方向上与每个接触孔紧邻的接触孔，并且触点的顶表面与衬底处于相同的高度。