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    INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220208966A1

    公开(公告)日：2022-06-30

    申请号：US17699609

    申请日：2022-03-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hwi-Chan JUN ,  Heon-jong Shin ,  In-Chan Hwang ,  Jae-ran Jang

    IPC: H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78

    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160049394A1

    公开(公告)日：2016-02-18

    申请号：US14629249

    申请日：2015-02-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heon-Jong SHIN ,  Deok-Han BAE ,  Dae-Hee WEON ,  Hwi-Chan JUN

    IPC: H01L27/088 ,  H01L29/417 ,  H01L23/532 ,  H01L29/45 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L27/0886 ,  H01L21/76804 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a transistor formed on a substrate and including a gate electrode and a source/drain, an interlayer insulating layer covering the transistor, a first contact hole formed in the interlayer insulating layer to expose a part of the transistor, a first barrier metal conformally formed on an inner surface of the first contact hole, a first conductive layer formed on the first barrier metal to fill the first contact hole, a second contact hole formed on the first conductive layer in the interlayer insulating layer and having a larger width than the first contact hole, a second barrier metal conformally formed on an inner surface of the second contact hole, and a second conductive layer formed on the second barrier metal to fill the second contact hole, wherein the second barrier metal is formed between the first conductive layer and the second conductive layer.

    Abstract translation: 半导体器件包括形成在衬底上并包括栅极和源极/漏极的晶体管，覆盖晶体管的层间绝缘层，形成在层间绝缘层中以暴露晶体管的一部分的第一接触孔，第一栅极 在第一接触孔的内表面上保形地形成的金属，形成在第一阻挡金属上以填充第一接触孔的第一导电层，形成在层间绝缘层中的第一导电层上并具有较大宽度的第二接触孔 形成在第二接触孔的内表面上的第二阻挡金属和形成在第二阻挡金属上以填充第二接触孔的第二导电层，其中第二阻挡金属形成在第一接触孔之间， 导电层和第二导电层。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160020303A1

    公开(公告)日：2016-01-21

    申请号：US14670324

    申请日：2015-03-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hwi-Chan JUN ,  Deok-Han BAE ,  Hyun-Seung SONG ,  Seung-Seok HA

    IPC: H01L29/66 ,  H01L21/321 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033

    CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656

    Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

    Abstract translation: 本公开的实施例涉及一种用于制造包括具有改善的电特性的场效应晶体管的半导体器件的方法。 根据本公开的实施例，可以使用设置在栅极部分上的金属硬掩模部分来有效地形成自对准接触插塞。 此外，通过使用金属硬掩模部分，可以提高用于形成自对准接触插塞的光刻胶掩模的工艺余量。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220336661A1

    公开(公告)日：2022-10-20

    申请号：US17857608

    申请日：2022-07-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD

    Inventor： Hyun-Seung SONG ,  Hyo-Jin KIM ,  Kyoung-Mi PARK ,  Hwi-Chan JUN ,  SeungSeok HA

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

    Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220102491A1

    公开(公告)日：2022-03-31

    申请号：US17038217

    申请日：2020-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hwi-Chan JUN ,  Heon-jong SHIN ,  In-chan HWANG ,  Jae-ran JANG

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L29/40 ,  H01L21/8234

    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

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