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1.发明授权公开(公告)号：US11798629B2
公开(公告)日：2023-10-24
申请号：US17489988
申请日：2021-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC: G11C7/14 , G11C16/10 , G11C16/08 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04 , H10B41/27 , H10B43/27
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/349 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H10B43/27 , H01L2224/05147 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US11061769B2
公开(公告)日：2021-07-13
申请号：US16851434
申请日：2020-04-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Duk Yu , Jin-Young Kim
Abstract: A storage device includes a first nonvolatile memory chip; a second nonvolatile memory chip; and a controller. The controller may include a processor configured to execute a flash translation layer (FTL) loaded onto an on-chip memory; an ECC engine configured to generate first parity bits for data and to selectively generate second parity bits for the data, under control of the processor; and a nonvolatile memory interface circuit configured to transmit the data and the first parity bits to the first nonvolatile memory chip, and to selectively transmit the second parity bits selectively generated to the second nonvolatile memory chip.
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3.发明授权公开(公告)号：US11043274B2
公开(公告)日：2021-06-22
申请号：US16851622
申请日：2020-04-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
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公开(公告)号：US09478280B2
公开(公告)日：2016-10-25
申请号：US14742726
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Duk Yu , Dong-Ku Kang , Dae-Yeal Lee
CPC classification number: G11C11/5628 , G11C5/143 , G11C16/10 , G11C16/3454 , G11C16/3459
Abstract: A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data. A control logic unit includes a verification operation controller configured to selectively perform, based on a result of comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.
Abstract translation: 半导体存储器件被配置为通过将验证电压的初始电压电平设置为第一电压电平并在第一时段期间提高验证电压来执行第一验证操作。 半导体存储器件包括存储程序数据的存储单元阵列，产生检测数据的传感器和比较程序数据和检测数据的条件确定单元。 控制逻辑单元包括验证操作控制器，被配置为基于程序数据和感测数据的比较结果选择性地执行用于通过将初始电压电平设置为第二电压来控制第二验证操作的第一验证控制操作 并且在第二时段期间增强验证电压，以及第二验证控制操作，用于通过将初始电压电平设置为第一电压电平来控制第二验证操作，并在第一时段期间升高验证电压。
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公开(公告)号：US11532365B2
公开(公告)日：2022-12-20
申请号：US17377141
申请日：2021-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Duk Yu , Sang-Wan Nam , Jonghoon Park , Ho-Jun Lee
Abstract: An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20210065805A1
公开(公告)日：2021-03-04
申请号：US16851622
申请日：2020-04-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
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7.发明授权公开(公告)号：US11158379B2
公开(公告)日：2021-10-26
申请号：US16935535
申请日：2020-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC: G11C16/10 , G11C16/04 , G11C16/08 , G11C16/26 , G11C7/10 , G11C7/22 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11582 , H01L27/11556
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US11106368B2
公开(公告)日：2021-08-31
申请号：US16458692
申请日：2019-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Duk Yu , Jin-Young Kim , Yu-Hun Jun
Abstract: A solid state drive and a method for accessing the metadata are provided. The solid state drive includes different kinds of first and second memories and a memory controller which controls the first and second memories, wherein the memory controller receives a metadata access request from a host, and includes a condition checker which determines conditions of the first and second memories in response to the metadata access request and selects at least one of the conditions, and the memory controller accesses to the memory selected by the condition checker.
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公开(公告)号：US10942678B2
公开(公告)日：2021-03-09
申请号：US16292769
申请日：2019-03-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Young Kim , Jae-Duk Yu , Yu-Hun Jun
IPC: G06F3/06
Abstract: A method of accessing data in a storage device including first and second nonvolatile memories of different types is provided. The method includes setting a meta data attribute table by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detecting a data attribute of first meta data among the plurality of meta data based on the meta data attribute table in response to receiving a first access request for the first meta data, determining a target memory optimized for the first meta data from among the first and second nonvolatile memories based on the detected data attribute of the first meta data, and performing an access operation on the target memory based on the first meta data. The plurality of meta data are used for controlling an operation of the storage device.
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10.发明申请公开(公告)号：US20210065806A1
公开(公告)日：2021-03-04
申请号：US16935535
申请日：2020-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC: G11C16/10 , G11C16/04 , G11C16/08 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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