公开(公告)号：US20250087264A1

公开(公告)日：2025-03-13

申请号：US18958240

申请日：2024-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US20240233844A1

公开(公告)日：2024-07-11

申请号：US18471430

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunchan Lee ,  Jungyu Lee ,  Yumin Kim ,  Jihyun Park ,  Jayang Yoon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: A device includes a first current mirror circuit including a plurality of first transistors, the plurality of first transistors including a common gate configured to receive a decoding signal according to a number of fail bits that are program-failed, a second current mirror circuit including a plurality of second transistors including a common gate configured to receive a reference current signal and a plurality of resistors respectively electrically connected to respective first terminals of the second transistors, and a comparison circuit configured to determine a compared result by comparing a first voltage corresponding to the decoding signal with respective ones of a plurality of second voltages output from the second current mirror circuit and configured to output a count signal corresponding to the compared result.

公开(公告)号：US12190942B2

公开(公告)日：2025-01-07

申请号：US17863037

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US20240242765A1

公开(公告)日：2024-07-18

申请号：US18382325

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jayang Yoon ,  Chihyun Kim ,  Sangsoo Park ,  Junehong Park ,  Chiweon Yoon ,  Hyeongdo Choi

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/30

Abstract: A non-volatile memory device includes a memory cell array including memory cells coupled to word lines, a boost circuit that receives an external power supply voltage and generate a boosted voltage based on the external power supply voltage, a regulator that generates a regulated voltage based on the external power supply voltage, and a control logic that controls word line voltages provided to the word lines. The control logic performs plural program loops in a program operation for the memory cell array. The control logic provides an adjacent word line voltage to an adjacent word line that is adjacent to a selected word line. In a first section of the program loops, the control logic provides the regulated voltage as the adjacent word line voltage, and in a second section of the program loops, the control logic provides the boosted voltage as the adjacent word line voltage.

公开(公告)号：US20240194273A1

公开(公告)日：2024-06-13

申请号：US18239480

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chiweon Yoon ,  Chihyun Kim ,  Philkyu Kang ,  Junehong Park ,  Jayang Yoon ,  Hyeongdo Choi

IPC: G11C16/30 ,  G06F1/20 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/30 ,  G06F1/206 ,  G11C16/0483 ,  G11C16/08

Abstract: A nonvolatile memory device comprising a charge pump circuit with pump units connected in series that receives an external voltage for charge pumping and outputs a pump voltage in stages according to stage control signals, a switching circuit that controls the charge pump circuit to output pumping voltages in response to switch control signals, a stage controller that outputs the stage control signals and the switch control signals based on a temperature code, and a digital temperature sensor that generates the temperature code.

公开(公告)号：US20230146885A1

公开(公告)日：2023-05-11

申请号：US17863037

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4099 ,  G11C11/4074 ,  G11C11/4085

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.