公开(公告)号：US09841672B2

公开(公告)日：2017-12-12

申请号：US14690073

申请日：2015-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Kwon Kang ,  Jae-Seok Yang ,  Sung-Wook Hwang ,  Dong-Gyun Kim ,  Ji-Young Jung

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.

公开(公告)号：US09874810B2

公开(公告)日：2018-01-23

申请号：US15135041

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Young Jung ,  Dae-Kwon Kang ,  Dong-Gyun Kim ,  Jae-Seok Yang ,  Sung-Wook Hwang

IPC: G06F17/50 ,  G03F1/70 ,  G03F1/68

CPC classification number: G03F1/70 ,  G03F1/68

Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

公开(公告)号：US09652578B2

公开(公告)日：2017-05-16

申请号：US14674416

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Gyun Kim ,  Sung-Wook Hwang ,  Dae-Kwon Kang ,  Jae-Seok Yang ,  Ji-Young Jung

IPC: G06F17/50 ,  H01L27/02 ,  H01L21/308

CPC classification number: G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/3086 ,  H01L27/0207

Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.

公开(公告)号：US20160313638A1

公开(公告)日：2016-10-27

申请号：US15135041

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Young Jung ,  Dae-Kwon KANG ,  Dong-Gyun KIM ,  Jae-Seok YANG ,  Sung-Wook HWANG

IPC: G03F1/70 ,  G06F17/50

CPC classification number: G03F1/70 ,  G03F1/68

Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

Abstract translation: 提供了一种布局分解方法，其可以包括建筑物，包括多个节点和边缘的图形，所述布局设计包括多个多边形，其中所述节点对应于所述布局设计的所述多边形，并且所述边缘标识靠近 彼此距离多个节点之间的距离小于最小距离，将所述多个节点的度数与参考值进行比较，选择目标节点，其程度超过所述参考值，基于所述参考值识别第一和第二子图，基于 目标节点，在第一和第二子图上执行多图案化技术分解以获取第一和第二结果，以及创建对应于布局设计的一部分的第一掩模布局数据和对应于布局设计的另一部分的第二掩模布局数据 结合第一和​​第二结果的布局设计。

公开(公告)号：US08999748B2

公开(公告)日：2015-04-07

申请号：US13670001

申请日：2012-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Young Jung ,  Joo-Young Kim ,  Hyeok Kim

IPC: H01L51/40 ,  H01L29/08 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

CPC classification number: H01L51/0004 ,  H01L51/0005 ,  H01L51/0533 ,  H01L51/102

Abstract: According to example embodiments, a method of manufacturing an organic thin film transistor includes sequentially forming a gate electrode, a gate insulator, a source electrode, and a drain electrode on a substrate, forming a first self-assembled monolayer on the source electrode and the drain electrode from a first self-assembled monolayer precursor, forming a second self-assembled monolayer on the gate insulator from a second self-assembled monolayer precursor that is different from the first self-assembled monolayer precursor, and forming an organic semiconductor on the first self-assembled monolayer and the second self-assembled monolayer. The first self-assembled monolayer and the second self-assembled monolayer may be formed simultaneously or sequentially in a single container. An organic thin film transistor may be manufactured according to the method. A display device may include the organic thin film transistor.

Abstract translation: 根据示例性实施例，制造有机薄膜晶体管的方法包括在基板上依次形成栅电极，栅极绝缘体，源电极和漏电极，在源极上形成第一自组装单层， 漏电极从第一自组装单层前体形成，在第二自组装单层前体上形成第二自组装单层，该第二自组装单层前体与第一自组装单层前体不同，并在第一自组装单层前体上形成有机半导体 自组装单层和第二自组装单层。 第一自组装单层和第二自组装单层可以在单个容器中同时或顺序形成。 可以根据该方法制造有机薄膜晶体管。 显示装置可以包括有机薄膜晶体管。